Merge branch 'master' of github.com:ucb-bar/riscv-tests

[riscv-tests.git] / isa / rv64uv / sb.S

diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
index 9155de9a1584f9836e1f08520e05f74ea5798f12..b9954edd76a66912da4cf5d465f2645601feb41d 100644 (file)
--- a/isa/rv64uv/sb.S
+++ b/isa/rv64uv/sb.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   srl a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8