sigh, no wrap - use direct

[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb / test.py

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 4a8658020c8d61f96b3b3b54f2bbc7045898897e..810be3e895e504e4593cace00361169da3f6d1d6 100644 (file)
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -148,7 +148,7 @@ def wishbone_basic(dut):
 
     info = "Running Wishbone basic test"
     yield from setup_sim(dut, clk_period=clk_period, run=True)
-    master = yield from setup_jtag(wrap, tck_period = tck_period)
+    master = yield from setup_jtag(dut, tck_period = tck_period)
 
     # Load the memory address
     yield master.load_ir(cmd_MEMADDRESS)