add verilator post-pnr cocotb sim

[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb_v / Makefile

diff --git a/ls180/post_pnr/cocotb_v/Makefile b/ls180/post_pnr/cocotb_v/Makefile
new file mode 100644 (file)
index 0000000..b62b2b9
--- /dev/null
+++ b/ls180/post_pnr/cocotb_v/Makefile
@@ -0,0 +1,15 @@
+ifeq ($(SIM),)
+  $(error Use one of the run_*.sh scripts to run cocotb test bench)
+endif
+
+TOPLEVEL_LANG := verilog
+
+# copy chip.v from post_pnr ghdl "make chip"
+VERILOG_SOURCES := \
+  chip.v \
+# END VERILOG_SOURCES
+
+MODULE := test
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+