sort out build of chip/corona using experiments10_verilog

[soc-cocotb-sim.git] / ls180 / post_pnr / vhd2obj.py

diff --git a/ls180/post_pnr/vhd2obj.py b/ls180/post_pnr/vhd2obj.py
index afb485aa7b363570f38b47dddf6e08237d8e8922..ce3c9b82db839f5d4fad445da2dd979fc8966c57 100755 (executable)
--- a/ls180/post_pnr/vhd2obj.py
+++ b/ls180/post_pnr/vhd2obj.py
@@ -25,8 +25,8 @@ for srcdir, suffix in SRC:
         os.system("ghdl -a -g --std=08 ../%s/%s" % (srcdir, fname))
 
 # and chip and corona
-os.system("ghdl -a -g --std=08 ../chip_corona/chip_r.vhd")
-os.system("ghdl -a -g --std=08 ../chip_corona/corona_cts_r.vhd")
+#os.system("ghdl -a -g --std=08 ../chip_corona/chip_r.vhd")
+#os.system("ghdl -a -g --std=08 ../chip_corona/corona_cts_r.vhd")
 
 # back to original dir
 os.chdir(cwd)