get pre-coriolis2 verilator (wishbone) functional

[soc-cocotb-sim.git] / ls180 / pre_pnr / test.py

diff --git a/ls180/pre_pnr/test.py b/ls180/pre_pnr/test.py
index cb1611c66064fd27bf60eb3cc65b5b192f575cc4..9617edf27ba269329aea88a79c0fe554a7983c37 100644 (file)
--- a/ls180/pre_pnr/test.py
+++ b/ls180/pre_pnr/test.py
@@ -27,12 +27,12 @@ class DUTWrapper:
             ti = dut
         ti._discover_all()
         self.ti = ti
-        self.clk = ti.clk
-        self.rst = ti.rst
-        self.tck = ti.TAP_bus__tck
-        self.tms = ti.TAP_bus__tms
-        self.tdi = ti.TAP_bus__tdi
-        self.tdo = ti.TAP_bus__tdo
+        self.clk = dut.sys_clk
+        self.rst = dut.sys_rst
+        self.tck = dut.jtag_tck
+        self.tms = dut.jtag_tms
+        self.tdi = dut.jtag_tdi
+        self.tdo = dut.jtag_tdo
 
     def info(self, *args, **kwargs):
         return self.dut._log.info(*args, **kwargs)
@@ -152,8 +152,9 @@ def setup_jtag(wrap, *, tck_period):
     if False:
         # Yield is never executed but it makes this function a generator
         yield Timer(0)
+    clk_steps = get_sim_steps(tck_period, "ns")
     return JTAG_Master(wrap.tck, wrap.tms, wrap.tdi, wrap.tdo,
-                       clk_period=tck_period,
+                       clk_period=clk_steps,
                        ir_width=4)
 
 def execute_svf(wrap, *, jtag, svf_filename):