whitespace cleanup

[nmigen-soc.git] / nmigen_soc / test / test_wishbone_bus.py

diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 63d410950403dbbbd9060067fa712dffacf70a04..7360edc8d1a0a5f6c6810bd1eada6e4acd8a26fc 100644 (file)
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -47,7 +47,8 @@ class InterfaceTestCase(unittest.TestCase):
 
     def test_features(self):
         iface = Interface(addr_width=32, data_width=32,
-                          features={"rty", "err", "stall", "lock", "cti", "bte"})
+                          features={"rty", "err", "stall", "lock",
+                                     "cti", "bte"})
         self.assertEqual(iface.layout, Layout.cast([
             ("adr",   32, DIR_FANOUT),
             ("dat_w", 32, DIR_FANOUT),
@@ -104,32 +105,40 @@ class DecoderTestCase(unittest.TestCase):
 
     def test_add_wrong(self):
         with self.assertRaisesRegex(TypeError,
-                r"Subordinate bus must be an instance of wishbone\.Interface, not 'foo'"):
+                r"Subordinate bus must be an instance of "
+                r"wishbone\.Interface, not 'foo'"):
             self.dut.add("foo")
 
     def test_add_wrong_granularity(self):
         with self.assertRaisesRegex(ValueError,
                 r"Subordinate bus has granularity 32, which is greater than "
                 r"the decoder granularity 16"):
-            self.dut.add(Interface(addr_width=15, data_width=32, granularity=32))
+            self.dut.add(Interface(addr_width=15, data_width=32,
+                                   granularity=32))
 
     def test_add_wrong_width_dense(self):
         with self.assertRaisesRegex(ValueError,
-                r"Subordinate bus has data width 16, which is not the same as decoder "
+                r"Subordinate bus has data width 16, which is not the "
+                r"same as decoder "
                 r"data width 32 \(required for dense address translation\)"):
-            self.dut.add(Interface(addr_width=15, data_width=16, granularity=16))
+            self.dut.add(Interface(addr_width=15, data_width=16,
+                                   granularity=16))
 
     def test_add_wrong_granularity_sparse(self):
         with self.assertRaisesRegex(ValueError,
-                r"Subordinate bus has data width 64, which is not the same as subordinate "
-                r"bus granularity 16 \(required for sparse address translation\)"):
-            self.dut.add(Interface(addr_width=15, data_width=64, granularity=16), sparse=True)
+                r"Subordinate bus has data width 64, which is not the same "
+                r"as subordinate bus granularity 16 \(required for "
+                r"sparse address translation\)"):
+            self.dut.add(Interface(addr_width=15, data_width=64,
+                                   granularity=16), sparse=True)
 
     def test_add_wrong_optional_output(self):
         with self.assertRaisesRegex(ValueError,
-                r"Subordinate bus has optional output 'err', but the decoder does "
+                r"Subordinate bus has optional output 'err', "
+                r"but the decoder does "
                 r"not have a corresponding input"):
-            self.dut.add(Interface(addr_width=15, data_width=32, granularity=16, features={"err"}))
+            self.dut.add(Interface(addr_width=15, data_width=32,
+                                    granularity=16, features={"err"}))
 
 
 class DecoderSimulationTestCase(unittest.TestCase):
@@ -140,7 +149,8 @@ class DecoderSimulationTestCase(unittest.TestCase):
         self.assertEqual(dut.add(sub_1, addr=0x10000),
                          (0x10000, 0x20000, 1))
         sub_2 = Interface(addr_width=14, data_width=32, granularity=8,
-                          features={"err", "rty", "stall", "lock", "cti", "bte"})
+                          features={"err", "rty", "stall", "lock",
+                                    "cti", "bte"})
         self.assertEqual(dut.add(sub_2),
                          (0x20000, 0x30000, 1))
 
@@ -228,7 +238,8 @@ class DecoderSimulationTestCase(unittest.TestCase):
 
                 for index, sel_bit in enumerate(self.bus.sel):
                     with m.If(sel_bit):
-                        segment = self.bus.dat_r.word_select(index, self.bus.granularity)
+                        segment = self.bus.dat_r.word_select(index,
+                                                    self.bus.granularity)
                         m.d.comb += segment.eq(self.bus.adr + index)
 
                 return m
@@ -338,30 +349,37 @@ class ArbiterTestCase(unittest.TestCase):
 
     def test_add_wrong(self):
         with self.assertRaisesRegex(TypeError,
-                r"Initiator bus must be an instance of wishbone\.Interface, not 'foo'"):
+                r"Initiator bus must be an instance of "
+                r"wishbone\.Interface, not 'foo'"):
             self.dut.add("foo")
 
     def test_add_wrong_addr_width(self):
         with self.assertRaisesRegex(ValueError,
-                r"Initiator bus has address width 15, which is not the same as arbiter "
+                r"Initiator bus has address width 15, which is "
+                r"not the same as arbiter "
                 r"address width 31"):
-            self.dut.add(Interface(addr_width=15, data_width=32, granularity=16))
+            self.dut.add(Interface(addr_width=15, data_width=32,
+                                   granularity=16))
 
     def test_add_wrong_granularity(self):
         with self.assertRaisesRegex(ValueError,
                 r"Initiator bus has granularity 8, which is lesser than "
                 r"the arbiter granularity 16"):
-            self.dut.add(Interface(addr_width=31, data_width=32, granularity=8))
+            self.dut.add(Interface(addr_width=31, data_width=32,
+                                   granularity=8))
 
     def test_add_wrong_data_width(self):
         with self.assertRaisesRegex(ValueError,
-                r"Initiator bus has data width 16, which is not the same as arbiter "
+                r"Initiator bus has data width 16, which is not "
+                r"the same as arbiter "
                 r"data width 32"):
-            self.dut.add(Interface(addr_width=31, data_width=16, granularity=16))
+            self.dut.add(Interface(addr_width=31, data_width=16,
+                                   granularity=16))
 
     def test_add_wrong_optional_output(self):
         with self.assertRaisesRegex(ValueError,
-                r"Initiator bus has optional output 'lock', but the arbiter does "
+                r"Initiator bus has optional output 'lock', but "
+                r"the arbiter does "
                 r"not have a corresponding input"):
             self.dut.add(Interface(addr_width=31, data_width=32, granularity=16,
                                    features={"lock"}))
@@ -374,7 +392,8 @@ class ArbiterSimulationTestCase(unittest.TestCase):
         itor_1 = Interface(addr_width=30, data_width=32, granularity=8)
         dut.add(itor_1)
         itor_2 = Interface(addr_width=30, data_width=32, granularity=16,
-                           features={"err", "rty", "stall", "lock", "cti", "bte"})
+                           features={"err", "rty", "stall", "lock",
+                                   "cti", "bte"})
         dut.add(itor_2)
 
         def sim_test():