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autopep8 cleanup
[nmigen-soc.git] / nmigen_soc / test / test_wishbone_bus.py
diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 7360edc8d1a0a5f6c6810bd1eada6e4acd8a26fc..d93ea9d54ae6757dd3cd393df4eebaf80b9e5dd7 100644 (file)
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -17,14 +17,14 @@ class InterfaceTestCase(unittest.TestCase):
         self.assertEqual(iface.memory_map.addr_width, 32)
         self.assertEqual(iface.memory_map.data_width, 8)
         self.assertEqual(iface.layout, Layout.cast([
-            ("adr",   32, DIR_FANOUT),
-            ("dat_w", 8,  DIR_FANOUT),
-            ("dat_r", 8,  DIR_FANIN),
-            ("sel",   1,  DIR_FANOUT),
-            ("cyc",   1,  DIR_FANOUT),
-            ("stb",   1,  DIR_FANOUT),
-            ("we",    1,  DIR_FANOUT),
-            ("ack",   1,  DIR_FANIN),
+            ("adr", 32, DIR_FANOUT),
+            ("dat_w", 8, DIR_FANOUT),
+            ("dat_r", 8, DIR_FANIN),
+            ("sel", 1, DIR_FANOUT),
+            ("cyc", 1, DIR_FANOUT),
+            ("stb", 1, DIR_FANOUT),
+            ("we", 1, DIR_FANOUT),
+            ("ack", 1, DIR_FANIN),
         ]))
 
     def test_granularity(self):
@@ -35,35 +35,35 @@ class InterfaceTestCase(unittest.TestCase):
         self.assertEqual(iface.memory_map.addr_width, 32)
         self.assertEqual(iface.memory_map.data_width, 8)
         self.assertEqual(iface.layout, Layout.cast([
-            ("adr",   30, DIR_FANOUT),
+            ("adr", 30, DIR_FANOUT),
             ("dat_w", 32, DIR_FANOUT),
             ("dat_r", 32, DIR_FANIN),
-            ("sel",   4,  DIR_FANOUT),
-            ("cyc",   1,  DIR_FANOUT),
-            ("stb",   1,  DIR_FANOUT),
-            ("we",    1,  DIR_FANOUT),
-            ("ack",   1,  DIR_FANIN),
+            ("sel", 4, DIR_FANOUT),
+            ("cyc", 1, DIR_FANOUT),
+            ("stb", 1, DIR_FANOUT),
+            ("we", 1, DIR_FANOUT),
+            ("ack", 1, DIR_FANIN),
         ]))
 
     def test_features(self):
         iface = Interface(addr_width=32, data_width=32,
                           features={"rty", "err", "stall", "lock",
-                                     "cti", "bte"})
+                                    "cti", "bte"})
         self.assertEqual(iface.layout, Layout.cast([
-            ("adr",   32, DIR_FANOUT),
+            ("adr", 32, DIR_FANOUT),
             ("dat_w", 32, DIR_FANOUT),
             ("dat_r", 32, DIR_FANIN),
-            ("sel",   1,  DIR_FANOUT),
-            ("cyc",   1,  DIR_FANOUT),
-            ("stb",   1,  DIR_FANOUT),
-            ("we",    1,  DIR_FANOUT),
-            ("ack",   1,  DIR_FANIN),
-            ("err",   1,  DIR_FANIN),
-            ("rty",   1,  DIR_FANIN),
-            ("stall", 1,  DIR_FANIN),
-            ("lock",  1,  DIR_FANOUT),
-            ("cti",   CycleType,    DIR_FANOUT),
-            ("bte",   BurstTypeExt, DIR_FANOUT),
+            ("sel", 1, DIR_FANOUT),
+            ("cyc", 1, DIR_FANOUT),
+            ("stb", 1, DIR_FANOUT),
+            ("we", 1, DIR_FANOUT),
+            ("ack", 1, DIR_FANIN),
+            ("err", 1, DIR_FANIN),
+            ("rty", 1, DIR_FANIN),
+            ("stall", 1, DIR_FANIN),
+            ("lock", 1, DIR_FANOUT),
+            ("cti", CycleType, DIR_FANOUT),
+            ("bte", BurstTypeExt, DIR_FANOUT),
         ]))
 
     def test_wrong_addr_width(self):
@@ -138,7 +138,7 @@ class DecoderTestCase(unittest.TestCase):
                 r"but the decoder does "
                 r"not have a corresponding input"):
             self.dut.add(Interface(addr_width=15, data_width=32,
-                                    granularity=16, features={"err"}))
+                                   granularity=16, features={"err"}))
 
 
 class DecoderSimulationTestCase(unittest.TestCase):
@@ -239,7 +239,7 @@ class DecoderSimulationTestCase(unittest.TestCase):
                 for index, sel_bit in enumerate(self.bus.sel):
                     with m.If(sel_bit):
                         segment = self.bus.dat_r.word_select(index,
-                                                    self.bus.granularity)
+                                                             self.bus.granularity)
                         m.d.comb += segment.eq(self.bus.adr + index)
 
                 return m
@@ -254,7 +254,7 @@ class DecoderSimulationTestCase(unittest.TestCase):
         loop_3 = AddressLoopback(addr_width=8, data_width=16, granularity=16)
         self.assertEqual(dut.add(loop_3.bus, addr=0x30000, sparse=True),
                          (0x30000, 0x30100, 1))
-        loop_4 = AddressLoopback(addr_width=8, data_width=8,  granularity=8)
+        loop_4 = AddressLoopback(addr_width=8, data_width=8, granularity=8)
         self.assertEqual(dut.add(loop_4.bus, addr=0x40000, sparse=True),
                          (0x40000, 0x40100, 1))
 
@@ -393,7 +393,7 @@ class ArbiterSimulationTestCase(unittest.TestCase):
         dut.add(itor_1)
         itor_2 = Interface(addr_width=30, data_width=32, granularity=16,
                            features={"err", "rty", "stall", "lock",
-                                   "cti", "bte"})
+                                     "cti", "bte"})
         dut.add(itor_2)
 
         def sim_test():
@@ -618,39 +618,39 @@ class InterconnectSharedSimulationTestCase(unittest.TestCase):
         self.shared = Interface(addr_width=30,
                                 data_width=32,
                                 granularity=8,
-                                features={"err","cti","bte"},
+                                features={"err", "cti", "bte"},
                                 name="shared")
         self.master01 = Interface(addr_width=30,
                                   data_width=32,
                                   granularity=8,
-                                  features={"err","cti","bte"},
+                                  features={"err", "cti", "bte"},
                                   name="master01")
         self.master02 = Record([
-            ("adr",   30, DIR_FANOUT),
+            ("adr", 30, DIR_FANOUT),
             ("dat_w", 32, DIR_FANOUT),
             ("dat_r", 32, DIR_FANIN),
-            ("sel",    4, DIR_FANOUT),
-            ("cyc",    1, DIR_FANOUT),
-            ("stb",    1, DIR_FANOUT),
-            ("ack",    1, DIR_FANIN),
-            ("we",     1, DIR_FANOUT),
-            ("cti",    3, DIR_FANOUT),
-            ("bte",    2, DIR_FANOUT),
-            ("err",    1, DIR_FANIN)
+            ("sel", 4, DIR_FANOUT),
+            ("cyc", 1, DIR_FANOUT),
+            ("stb", 1, DIR_FANOUT),
+            ("ack", 1, DIR_FANIN),
+            ("we", 1, DIR_FANOUT),
+            ("cti", 3, DIR_FANOUT),
+            ("bte", 2, DIR_FANOUT),
+            ("err", 1, DIR_FANIN)
         ])
         self.sub01 = Interface(addr_width=11,
-                             data_width=32,
-                             granularity=8,
-                             features={"err","cti","bte"},
-                             name="sub01")
+                               data_width=32,
+                               granularity=8,
+                               features={"err", "cti", "bte"},
+                               name="sub01")
         self.sub02 = Interface(addr_width=21,
                                data_width=32,
                                granularity=8,
-                               features={"err","cti","bte"},
+                               features={"err", "cti", "bte"},
                                name="sub02")
         self.dut = InterconnectShared(
             addr_width=30, data_width=32, granularity=8,
-            features={"err","cti","bte"},
+            features={"err", "cti", "bte"},
             itors=[
                 self.master01,
                 self.master02