wishbone: fix SRAM; improve tests for Decoder & Arbiter

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index 84faeeda80f7d98b68e6d1565e380e5be1397e23..de5c15d551c081a224590ee4ba8706ca3d2d7547 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -47,15 +47,8 @@ class SRAM(Elaboratable):
                             .format(memory))
         self.memory = memory
         self.read_only = read_only
-        # Define total address space:
-        # - Base: equals memory.depth
-        # - Has an additional ReadPort: add rdport.depth
-        # - Has an additional WirtePort: add wrport.depth
-        self._memdepth = self.memory.depth * 2
-        if not read_only:
-            self._memdepth += self.memory.depth
         if bus is None:
-            bus = Interface(addr_width=max(0, log2_int(self._memdepth, need_pow2=False)),
+            bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,