whitespace cleanup

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index de5c15d551c081a224590ee4ba8706ca3d2d7547..eeeada3cc99c97c4eb246f2d3c7612a7b1bba5e2 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -8,12 +8,14 @@ __all__ = ["SRAM"]
 
 
 class SRAM(Elaboratable):
-    """SRAM module carrying a volatile memory block (implemented with :class:`Memory`)
-    that can be read and write (or only read if the SRAM is read-only) through a Wishbone bus.
+    """SRAM module carrying a volatile memory block (implemented with
+    :class:`Memory`) that can be read and write (or only read if the
+    SRAM is read-only) through a Wishbone bus.
 
-    If no Wishbone bus is specified during initialisation, this creates one whose address width
-    is just enough to fit the whole memory (i.e. equals to the log2(memory depth) rounded up), and
-    whose data width is equal to the memory width.
+    If no Wishbone bus is specified during initialisation, this creates
+    one whose address width is just enough to fit the whole memory
+    (i.e. equals to the log2(memory depth) rounded up), and whose data
+    width is equal to the memory width.
 
     Parameters
     ----------
@@ -22,23 +24,25 @@ class SRAM(Elaboratable):
     read_only : bool
         Whether or not the memory is read-only. Defaults to False.
     bus : :class:`Interface` or None
-        The Wishbone bus interface providing access to the read/write ports of the memory.
-        Optional and defaults to None, which lets this module to instantiate one as described
-        above, having the granularity, features and alignment as specified by their
+        The Wishbone bus interface providing access to the read/write
+        ports of the memory.  Optional and defaults to None, which
+        lets this module to instantiate one as described above, having
+        the granularity, features and alignment as specified by their
         corresponding parameters.
     granularity : int or None
-        If the Wishbone bus is not sepcified, this is the granularity of the Wishbone bus.
-        Optional. See :class:`Interface`.
+        If the Wishbone bus is not sepcified, this is the granularity
+        of the Wishbone bus.  Optional. See :class:`Interface`.
     features : iter(str)
-        If the Wishbone bus is not sepcified, this is the optional signal set for the Wishbone bus.
-        See :class:`Interface`.
+        If the Wishbone bus is not sepcified, this is the optional signal
+        set for the Wishbone bus.  See :class:`Interface`.
 
     Attributes
     ----------
     memory : :class:`Memory`
         The memory to be accessed via the Wishbone bus.
     bus : :class:`Interface`
-        The Wishbone bus interface providing access to the read/write ports of the memory.
+        The Wishbone bus interface providing access to the read/write
+        ports of the memory.
     """
     def __init__(self, memory, read_only=False, bus=None,
                  granularity=None, features=frozenset()):
@@ -86,4 +90,4 @@ class SRAM(Elaboratable):
         with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
             m.d.sync += self.bus.ack.eq(1)
 
-        return m
\ No newline at end of file
+        return m