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[libreriscv.git] / openpower / sv / executive_summary.mdwn

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 3512ffcb471cea62eb538b167b7562feb592526b..3b298507bb4749e427dc76c0877019f060964260 100644 (file)
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -12,9 +12,9 @@ Power ISA.
 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
 instructions vertical and registers horizontal otherwise it will be
 difficult to grasp and appreciate its RISC simplicity.
-
 Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
-ubiquitous, the ISA uniform.
+ubiquitous, the ISA uniform. The Compliancy Levels offer a means
+to scale up in complexity to meet the target application requirements.
 
 * GPUs may implement massive-wide SIMD back-ends, focussing on
   number-crunching.
@@ -30,7 +30,7 @@ ecosystem)*.
 *If not done as carefully as SVP64, the addition of any other Scalable
 Vector Extension would require a significant number of opcodes, putting
 further pressure on Major Opcode space which was never designed with
-Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
+Scalable Vectors in mind.  Contrast with RISC-V which was
 designed over a 7 year period with Cray-style Vectors right from the start.*
 
 Even with this amount of time spent, SVP64 exceeds the capability of RVV.
@@ -44,8 +44,9 @@ Simple-V is **not RISC-V and is not RISC-V Vectors**.
 [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc),
 [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
 [MRISC32](https://github.com/mrisc32/mrisc32)
-are all based on Cray-style Scalable Vectors
-of 30 years ago, hence the similarity,
+are all based on
+[Cray-style Scalable Vectors](https://en.m.wikipedia.org/wiki/Cray-1)
+of 50 years ago, hence the similarity,
 the provision of a `setvl` instruction, and why they are each called
 "Scalable" Vectors, because it is the `setvl` instruction that
 presents the **programmer** with explicit control over Vector length.
@@ -54,7 +55,8 @@ VSX and NEON are PackedSIMD, and
 AVX-512 and ARM SVE2 are Predicated SIMD ISAs.
 **None of them provide Scalability to the Programmer**.  SVE2 is **Silicon**
 Scalable, not **Programmer** Scalable: the distinction is profoundly
-important (already causing problems).
+important (already
+[causing problems](https://bugs.libre-soc.org/show_bug.cgi?id=893#c15) ).
 For Predicated SIMD, Programmers must emulate Cray-style scaling
 through explicit predicate masking, which increases instruction count in
 hot-loops.
@@ -64,15 +66,11 @@ hot-loops.
 |---------------------------------------------------------------------------------------------|
 | **Unit tests and simulator for Power ISA v3.0 and SVP64**                                   |
 | <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD> |
-| - - -                                                                                       |
 | **pypowersim tutorial**                                                                     |
 | <https://libre-soc.org/docs/pypowersim/>                                                    |
-| - - -                                                                                       |
 | **several thousand more ISA unit tests**                                                    |
 |  <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>       |
-| - - -                                                                                       |
 | **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** |
 | <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>           |
-| - - -                                                                                       |
-| **binutils support for SVP64**                                                              |
+| **binutils support for DRAFT SVP64 (now upstream)**                                                              |
 | <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>            |