OpenOCD does a dmi read and gets dummy value back.

[riscv-isa-sim.git] / riscv / debug_module.cc

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 17b8b45fb13189993cace929b78545e5b67e5b97..318ef9692bf38c5cc67c3466b58aff39a0af1a0e 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -5,6 +5,12 @@
 
 #include "debug_rom/debug_rom.h"
 
+#if 1
+#  define D(x) x
+#else
+#  define D(x)
+#endif
+
 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
 {
   addr = DEBUG_START + addr;
@@ -19,7 +25,7 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
     return true;
   }
 
-  fprintf(stderr, "ERROR: invalid load from debug module: %ld bytes at 0x%016"
+  fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
           PRIx64 "\n", len, addr);
   return false;
 }
@@ -29,7 +35,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
   addr = DEBUG_START + addr;
 
   if (addr & (len-1)) {
-    fprintf(stderr, "ERROR: unaligned store to debug module: %ld bytes at 0x%016"
+    fprintf(stderr, "ERROR: unaligned store to debug module: %zd bytes at 0x%016"
             PRIx64 "\n", len, addr);
     return false;
   }
@@ -47,7 +53,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
     return true;
   }
 
-  fprintf(stderr, "ERROR: invalid store to debug module: %ld bytes at 0x%016"
+  fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
           PRIx64 "\n", len, addr);
   return false;
 }
@@ -72,3 +78,14 @@ uint32_t debug_module_t::ram_read32(unsigned int index)
     (((uint32_t) base[3]) << 24);
   return value;
 }
+
+uint32_t debug_module_t::dmi_read(unsigned address)
+{
+  D(fprintf(stderr, "dmi_read(0x%x)\n", address));
+  return 0xfeed;
+}
+
+void debug_module_t::dmi_write(unsigned address, uint32_t value)
+{
+  D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
+}