Use correct format codes for reg_t and size_t

[riscv-isa-sim.git] / riscv / debug_module.cc

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 17b8b45fb13189993cace929b78545e5b67e5b97..8bcc60eada8d9eb5fbbdd8833e2463a16ae72c09 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -19,7 +19,7 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
     return true;
   }
 
-  fprintf(stderr, "ERROR: invalid load from debug module: %ld bytes at 0x%016"
+  fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
           PRIx64 "\n", len, addr);
   return false;
 }
@@ -29,7 +29,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
   addr = DEBUG_START + addr;
 
   if (addr & (len-1)) {
-    fprintf(stderr, "ERROR: unaligned store to debug module: %ld bytes at 0x%016"
+    fprintf(stderr, "ERROR: unaligned store to debug module: %zd bytes at 0x%016"
             PRIx64 "\n", len, addr);
     return false;
   }
@@ -47,7 +47,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
     return true;
   }
 
-  fprintf(stderr, "ERROR: invalid store to debug module: %ld bytes at 0x%016"
+  fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
           PRIx64 "\n", len, addr);
   return false;
 }