[fesvr,xcc,sim] fixed multicore sim for akaros

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 7638de90b9926b45f72a376ada0a204d1ab886f8..496b31ad034e28237b541080ff28c66d6d94d8da 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -45,6 +45,7 @@ const int JUMP_ALIGN_BITS = 1;
 #define SR_VM    0x0000000000010000ULL
 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM)
 #define SR_IM_SHIFT 8
+#define IPI_IRQ 5
 #define TIMER_IRQ 7
 
 #define CAUSE_EXCCODE 0x000000FF