Some bugfixes for CSR reading and setting FS for fflags updates (#43)

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index f4d6b6ccddb8737a40cbcf64ec8445e5b3a45c83..6e544319ebcd03585ac2a16188f6355c9ea183b2 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -184,7 +184,10 @@ private:
 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
 
-#define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
+#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
+                               dirty_fp_state; \
+                               STATE.fflags |= softfloat_exceptionFlags; \
+                             } \
                              softfloat_exceptionFlags = 0; })
 
 #define sext32(x) ((sreg_t)(int32_t)(x))