Rip out RVC for now

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index b8a036b56e8a139294d60448ddc279539cb98227..7c99581a4e3b039922be57d9bb0b9f984759472f 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_DECODE_H
 #define _RISCV_DECODE_H
 
@@ -121,7 +123,7 @@ union insn_t
   btype_t btype;
   ltype_t ltype;
   ftype_t ftype;
-  uint32_t bits;
+  uint_fast32_t bits;
 };
 
 template <class T>
@@ -150,6 +152,8 @@ public:
   }
   write_port_t<T> write_port(size_t i)
   {
+    if (zero_reg)
+      const_cast<T&>(data[0]) = 0;
     return write_port_t<T>(data[i]);
   }
   const T& operator [] (size_t i) const
@@ -219,33 +223,17 @@ private:
 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 
-// RVC stuff
-
-#define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
-#define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
-#define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
-
-#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
-#define CRD XPR.write_port(CRD_REGNUM)
-#define CRS1 XPR[(insn.bits >> 10) & 0x1f]
-#define CRS2 XPR[(insn.bits >> 5) & 0x1f]
-#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5U ((insn.bits >> 5) & 0x1f)
-#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
-#define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
-#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
-#define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
-
-static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-#define rvc_rd_regmap rvc_rs1_regmap
-#define rvc_rs2b_regmap rvc_rs1_regmap
-static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-#define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
-#define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
-#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
-#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
-#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
+#define insn_length(x) \
+  (((x) & 0x03) < 0x03 ? 2 : \
+   ((x) & 0x1f) < 0x1f ? 4 : \
+   ((x) & 0x3f) < 0x3f ? 6 : \
+   8)
+
+#define set_pc(x) \
+  do { if ((x) & 3 /* For now... */) \
+         throw trap_instruction_address_misaligned; \
+       npc = (x); \
+     } while(0)
 
 // vector stuff
 #define VL vl