#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
-#define __STDC_LIMIT_MACROS
-#include <stdint.h>
+#if (-1 != ~0) || ((-1 >> 1) != -1)
+# error spike requires a two''s-complement c++ implementation
+#endif
+
+#include <cstdint>
#include <string.h>
-#include "pcr.h"
+#include <strings.h>
+#include "encoding.h"
#include "config.h"
-
-typedef int int128_t __attribute__((mode(TI)));
-typedef unsigned int uint128_t __attribute__((mode(TI)));
+#include "common.h"
+#include <cinttypes>
typedef int64_t sreg_t;
typedef uint64_t reg_t;
typedef uint64_t freg_t;
-const int OPCODE_BITS = 7;
-
-const int XPRID_BITS = 5;
-const int NXPR = 1 << XPRID_BITS;
+const int NXPR = 32;
+const int NFPR = 32;
-const int FPR_BITS = 64;
-const int FPRID_BITS = 5;
-const int NFPR = 1 << FPRID_BITS;
-
-const int IMM_BITS = 12;
-const int IMMLO_BITS = 7;
-const int TARGET_BITS = 25;
-const int FUNCT_BITS = 3;
-const int FUNCTR_BITS = 7;
-const int FFUNCT_BITS = 2;
-const int RM_BITS = 3;
-const int BIGIMM_BITS = 20;
-const int BRANCH_ALIGN_BITS = 1;
-const int JUMP_ALIGN_BITS = 1;
+#define X_RA 1
+#define X_SP 2
#define FP_RD_NE 0
#define FP_RD_0 1
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
-#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
-
-// note: bit fields are in little-endian order
-struct itype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- signed imm12 : IMM_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct btype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned immlo : IMMLO_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- signed immhi : IMM_BITS-IMMLO_BITS;
-};
-
-struct jtype_t
-{
- unsigned jump_opcode : OPCODE_BITS;
- signed target : TARGET_BITS;
-};
+#define insn_length(x) \
+ (((x) & 0x03) < 0x03 ? 2 : \
+ ((x) & 0x1f) < 0x1f ? 4 : \
+ ((x) & 0x3f) < 0x3f ? 6 : \
+ 8)
-struct rtype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned functr : FUNCTR_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ltype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned bigimm : BIGIMM_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ftype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned ffunct : FFUNCT_BITS;
- unsigned rm : RM_BITS;
- unsigned rs3 : FPRID_BITS;
- unsigned rs2 : FPRID_BITS;
- unsigned rs1 : FPRID_BITS;
- unsigned rd : FPRID_BITS;
-};
-
-union insn_t
-{
- itype_t itype;
- jtype_t jtype;
- rtype_t rtype;
- btype_t btype;
- ltype_t ltype;
- ftype_t ftype;
- uint32_t bits;
-};
-
-template <class T>
-class write_port_t
+typedef uint64_t insn_bits_t;
+class insn_t
{
public:
- write_port_t(T& _t) : t(_t) {}
- T& operator = (const T& rhs)
- {
- return t = rhs;
- }
- operator T()
- {
- return t;
- }
+ insn_t() = default;
+ insn_t(insn_bits_t bits) : b(bits) {}
+ insn_bits_t bits() { return b; }
+ int length() { return insn_length(b); }
+ int64_t i_imm() { return int64_t(b) >> 20; }
+ int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+ int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+ int64_t u_imm() { return int64_t(b) >> 12 << 12; }
+ int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
+ uint64_t rd() { return x(7, 5); }
+ uint64_t rs1() { return x(15, 5); }
+ uint64_t rs2() { return x(20, 5); }
+ uint64_t rs3() { return x(27, 5); }
+ uint64_t rm() { return x(12, 3); }
+ uint64_t csr() { return x(20, 12); }
+
+ int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
+ int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
+ int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(5, 1) << 5) + (x(2, 3) << 6) + (xs(12, 1) << 9); }
+ int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
+ int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
+ int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
+ int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
+ int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
+ int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
+ int64_t rvc_j_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(7, 6) << 6); }
+ int64_t rvc_b_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(10, 3) << 6); }
+ int64_t rvc_simm3() { return x(10, 3); }
+ uint64_t rvc_rd() { return rd(); }
+ uint64_t rvc_rs1() { return rd(); }
+ uint64_t rvc_rs2() { return x(2, 5); }
+ uint64_t rvc_rds() { return 8 + x(10, 3); }
+ uint64_t rvc_rs1s() { return 8 + x(7, 3); }
+ uint64_t rvc_rs2s() { return 8 + x(2, 3); }
private:
- T& t;
+ insn_bits_t b;
+ uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
+ uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
+ uint64_t imm_sign() { return xs(63, 1); }
};
+
template <class T, size_t N, bool zero_reg>
class regfile_t
{
public:
- void reset()
+ void write(size_t i, T value)
{
- memset(data, 0, sizeof(data));
- }
- write_port_t<T> write_port(size_t i)
- {
- return write_port_t<T>(data[i]);
+ if (!zero_reg || i != 0)
+ data[i] = value;
}
const T& operator [] (size_t i) const
{
- if (zero_reg)
- const_cast<T&>(data[0]) = 0;
return data[i];
}
private:
T data[N];
};
-#define throw_illegal_instruction \
- ({ if (utmode) throw trap_vector_illegal_instruction; \
- else throw trap_illegal_instruction; })
-
// helpful macros, etc
-#define RS1 XPR[insn.rtype.rs1]
-#define RS2 XPR[insn.rtype.rs2]
-#define RD XPR.write_port(insn.rtype.rd)
-#define RA XPR.write_port(1)
-#define FRS1 FPR[insn.ftype.rs1]
-#define FRS2 FPR[insn.ftype.rs2]
-#define FRS3 FPR[insn.ftype.rs3]
-#define FRD FPR.write_port(insn.ftype.rd)
-#define BIGIMM insn.ltype.bigimm
-#define SIMM insn.itype.imm12
-#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
-#define SHAMT (insn.itype.imm12 & 0x3F)
-#define SHAMTW (insn.itype.imm12 & 0x1F)
-#define TARGET insn.jtype.target
-#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
-#define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
-#define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
-#define RM ({ int rm = insn.ftype.rm; \
- if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
- if(rm > 4) throw_illegal_instruction; \
- rm; })
-
-#define xpr64 (xprlen == 64)
-
-#define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
-#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
-#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
-#ifndef RISCV_ENABLE_FPU
-# define require_fp throw trap_illegal_instruction
-#else
-# define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
+#define MMU (*p->get_mmu())
+#define STATE (*p->get_state())
+#define READ_REG(reg) STATE.XPR[reg]
+#define RS1 READ_REG(insn.rs1())
+#define RS2 READ_REG(insn.rs2())
+#define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
+#define WRITE_RD(value) WRITE_REG(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ #undef WRITE_REG
+ #define WRITE_REG(reg, value) ({ \
+ reg_t wdata = (value); /* value is a func with side-effects */ \
+ STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
+ STATE.XPR.write(reg, wdata); \
+ })
#endif
-#ifndef RISCV_ENABLE_VEC
-# define require_vector throw trap_illegal_instruction
+
+// RVC macros
+#define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value)
+#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
+#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
+#define RVC_RS1 READ_REG(insn.rvc_rs1())
+#define RVC_RS2 READ_REG(insn.rvc_rs2())
+#define RVC_RS1S READ_REG(insn.rvc_rs1s())
+#define RVC_RS2S READ_REG(insn.rvc_rs2s())
+#define RVC_SP READ_REG(X_SP)
+
+// FPU macros
+#define FRS1 STATE.FPR[insn.rs1()]
+#define FRS2 STATE.FPR[insn.rs2()]
+#define FRS3 STATE.FPR[insn.rs3()]
+#define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
+#define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
+#define do_write_frd(value) (STATE.FPR.write(insn.rd(), value), dirty_fp_state)
+
+#ifndef RISCV_ENABLE_COMMITLOG
+# define WRITE_FRD(value) do_write_frd(value)
#else
-# define require_vector \
- ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
- else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
- })
+# define WRITE_FRD(value) ({ \
+ freg_t wdata = (value); /* value may have side effects */ \
+ STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
+ do_write_frd(wdata); \
+ })
#endif
+
+#define SHAMT (insn.i_imm() & 0x3F)
+#define BRANCH_TARGET (pc + insn.sb_imm())
+#define JUMP_TARGET (pc + insn.uj_imm())
+#define RM ({ int rm = insn.rm(); \
+ if(rm == 7) rm = STATE.frm; \
+ if(rm > 4) throw trap_illegal_instruction(); \
+ rm; })
+
+#define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
-#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ set_fsr(fsr | \
- (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
+#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction()
+#define require_privilege(p) require(get_field(STATE.mstatus, MSTATUS_PRV) >= (p))
+#define require_rv64 require(xlen == 64)
+#define require_rv32 require(xlen == 32)
+#define require_extension(s) require(p->supports_extension(s))
+#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
+#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
+
+#define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
softfloat_exceptionFlags = 0; })
#define sext32(x) ((sreg_t)(int32_t)(x))
#define zext32(x) ((reg_t)(uint32_t)(x))
-#define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
-#define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
-
-// RVC stuff
-
-#define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
-#define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
-#define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
-
-#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
-#define CRD XPR.write_port(CRD_REGNUM)
-#define CRS1 XPR[(insn.bits >> 10) & 0x1f]
-#define CRS2 XPR[(insn.bits >> 5) & 0x1f]
-#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5U ((insn.bits >> 5) & 0x1f)
-#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
-#define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
-#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
-#define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
-
-static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-#define rvc_rd_regmap rvc_rs1_regmap
-#define rvc_rs2b_regmap rvc_rs1_regmap
-static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-#define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
-#define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
-#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
-#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
-#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-
-// vector stuff
-#define VL vl
-
-#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
-#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
-#define UT_RA(idx) uts[idx]->XPR.write_port(1)
-#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
-#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
-#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
-#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
- ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
-
-#define UT_LOOP_START for (int i=0;i<VL; i++) {
-#define UT_LOOP_END }
-#define UT_LOOP_RS1 UT_RS1(i)
-#define UT_LOOP_RS2 UT_RS2(i)
-#define UT_LOOP_RD UT_RD(i)
-#define UT_LOOP_RA UT_RA(i)
-#define UT_LOOP_FRS1 UT_FRS1(i)
-#define UT_LOOP_FRS2 UT_FRS2(i)
-#define UT_LOOP_FRS3 UT_FRS3(i)
-#define UT_LOOP_FRD UT_FRD(i)
-#define UT_LOOP_RM UT_RM(i)
-
-#define VEC_LOAD(dst, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- UT_LOOP_##dst = mmu.func(addr); \
- addr += inc; \
- UT_LOOP_END
-
-#define VEC_STORE(src, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- mmu.func(addr, UT_LOOP_##src); \
- addr += inc; \
- UT_LOOP_END
-
-enum vt_command_t
-{
- vt_command_stop,
-};
+#define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
+#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
+
+#define set_pc(x) \
+ do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
+ throw trap_instruction_address_misaligned(x); \
+ npc = sext_xlen(x); \
+ } while(0)
+
+#define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */
+
+#define validate_csr(which, write) ({ \
+ if (!STATE.serialized) return PC_SERIALIZE; \
+ STATE.serialized = false; \
+ unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \
+ unsigned csr_priv = get_field((which), 0x300); \
+ unsigned csr_read_only = get_field((which), 0xC00) == 3; \
+ if (((write) && csr_read_only) || my_priv < csr_priv) \
+ throw trap_illegal_instruction(); \
+ (which); })
#endif