# error spike requires a two''s-complement c++ implementation
#endif
-#define __STDC_LIMIT_MACROS
-#include <stdint.h>
+#include <cstdint>
#include <string.h>
#include "encoding.h"
#include "config.h"
#include "common.h"
#include <cinttypes>
-typedef int int128_t __attribute__((mode(TI)));
-typedef unsigned int uint128_t __attribute__((mode(TI)));
-
typedef int64_t sreg_t;
typedef uint64_t reg_t;
typedef uint64_t freg_t;
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+typedef uint64_t insn_bits_t;
class insn_t
{
public:
- uint32_t bits() { return b; }
- reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
- reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
- reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
- reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
- reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
- uint32_t rd() { return x(7, 5); }
- uint32_t rs1() { return x(15, 5); }
- uint32_t rs2() { return x(20, 5); }
- uint32_t rs3() { return x(27, 5); }
- uint32_t rm() { return x(12, 3); }
+ insn_t() = default;
+ insn_t(insn_bits_t bits) : b(bits) {}
+ insn_bits_t bits() { return b; }
+ int64_t i_imm() { return int64_t(b) >> 20; }
+ int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+ int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+ int64_t u_imm() { return int64_t(b) >> 12 << 12; }
+ int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
+ uint64_t rd() { return x(7, 5); }
+ uint64_t rs1() { return x(15, 5); }
+ uint64_t rs2() { return x(20, 5); }
+ uint64_t rs3() { return x(27, 5); }
+ uint64_t rm() { return x(12, 3); }
+ uint64_t csr() { return x(20, 12); }
private:
- uint32_t b;
- reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
- reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
+ insn_bits_t b;
+ uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
+ uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
+ uint64_t imm_sign() { return xs(63, 1); }
};
template <class T, size_t N, bool zero_reg>
}
void write(size_t i, T value)
{
- data[i] = value;
+ if (!zero_reg || i != 0)
+ data[i] = value;
}
const T& operator [] (size_t i) const
{
- if (zero_reg)
- const_cast<T&>(data[0]) = 0;
return data[i];
}
private:
// helpful macros, etc
#define MMU (*p->get_mmu())
-#define RS1 p->get_state()->XPR[insn.rs1()]
-#define RS2 p->get_state()->XPR[insn.rs2()]
-#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+#define STATE (*p->get_state())
+#define RS1 STATE.XPR[insn.rs1()]
+#define RS2 STATE.XPR[insn.rs2()]
+#define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
#ifdef RISCV_ENABLE_COMMITLOG
#undef WRITE_RD
#define WRITE_RD(value) ({ \
- bool in_spvr = p->get_state()->sr & SR_S; \
reg_t wdata = value; /* value is a func with side-effects */ \
- if (!in_spvr) \
- fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
- p->get_state()->XPR.write(insn.rd(), wdata); \
+ STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
+ STATE.XPR.write(insn.rd(), wdata); \
})
#endif
-#define FRS1 p->get_state()->FPR[insn.rs1()]
-#define FRS2 p->get_state()->FPR[insn.rs2()]
-#define FRS3 p->get_state()->FPR[insn.rs3()]
-#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+#define FRS1 STATE.FPR[insn.rs1()]
+#define FRS2 STATE.FPR[insn.rs2()]
+#define FRS3 STATE.FPR[insn.rs3()]
+#define WRITE_FRD(value) STATE.FPR.write(insn.rd(), value)
#ifdef RISCV_ENABLE_COMMITLOG
#undef WRITE_FRD
#define WRITE_FRD(value) ({ \
- bool in_spvr = p->get_state()->sr & SR_S; \
freg_t wdata = value; /* value is a func with side-effects */ \
- if (!in_spvr) \
- fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
- p->get_state()->FPR.write(insn.rd(), wdata); \
+ STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
+ STATE.FPR.write(insn.rd(), wdata); \
})
#endif
-
-
#define SHAMT (insn.i_imm() & 0x3F)
#define BRANCH_TARGET (pc + insn.sb_imm())
#define JUMP_TARGET (pc + insn.uj_imm())
#define RM ({ int rm = insn.rm(); \
- if(rm == 7) rm = p->get_state()->frm; \
+ if(rm == 7) rm = STATE.frm; \
if(rm > 4) throw trap_illegal_instruction(); \
rm; })
#define xpr64 (xprlen == 64)
-#define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
+#define require_supervisor if(unlikely(!(STATE.sr & SR_S))) throw trap_privileged_instruction()
#define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
#define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
#ifndef RISCV_ENABLE_FPU
# define require_fp throw trap_illegal_instruction()
#else
-# define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
+# define require_fp if(unlikely(!(STATE.sr & SR_EF))) throw trap_fp_disabled()
#endif
-#define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
+#define require_accelerator if(unlikely(!(STATE.sr & SR_EA))) throw trap_accelerator_disabled()
#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ p->get_state()->fflags |= softfloat_exceptionFlags; \
+#define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
softfloat_exceptionFlags = 0; })
#define sext32(x) ((sreg_t)(int32_t)(x))
#define set_pc(x) \
do { if ((x) & 3 /* For now... */) \
- throw trap_instruction_address_misaligned(); \
- npc = (x); \
+ throw trap_instruction_address_misaligned(x); \
+ npc = sext_xprlen(x); \
} while(0)
#define validate_csr(which, write) ({ \
- int read_priv = ((which) >> 10) & 3; \
- int write_priv = ((which) >> 8) & 3; \
- if (read_priv > 0 || (write_priv > 0 && (write))) require_supervisor; \
+ unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \
+ unsigned read_priv = ((which) >> 10) & 3; \
+ unsigned write_priv = (((which) >> 8) & 3); \
+ if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
+ if (my_priv < ((write) ? write_priv : read_priv)) \
+ throw trap_privileged_instruction(); \
(which); })
#endif
projects / riscv-isa-sim.git / blobdiff