Generate instruction decoder dynamically

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 202541fbc79cb6539320585be0ac682a08b5fa09..be7d64d3db312c274ef2d382f6cd43ab2e314e04 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1,8 +1,11 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_DECODE_H
 #define _RISCV_DECODE_H
 
 #define __STDC_LIMIT_MACROS
 #include <stdint.h>
+#include <string.h>
 #include "pcr.h"
 #include "config.h"
 
@@ -120,10 +123,9 @@ union insn_t
   btype_t btype;
   ltype_t ltype;
   ftype_t ftype;
-  uint32_t bits;
+  uint_fast32_t bits;
 };
 
-#include <stdio.h>
 template <class T>
 class write_port_t
 {
@@ -150,6 +152,8 @@ public:
   }
   write_port_t<T> write_port(size_t i)
   {
+    if (zero_reg)
+      const_cast<T&>(data[0]) = 0;
     return write_port_t<T>(data[i]);
   }
   const T& operator [] (size_t i) const
@@ -183,6 +187,8 @@ private:
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
+#define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
+#define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
 #define RM ({ int rm = insn.ftype.rm; \
               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
               if(rm > 4) throw_illegal_instruction; \