Fix single stepping over faulting instructions. (#80)

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 36e789629ecc4d075e5b0681e3519892e5f1328b..eb9fe4bd9ac109929ca5784905c6adb21e45f778 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -190,6 +190,11 @@ miss:
     {
       take_trap(t, pc);
       n = instret;
+
+      if (unlikely(state.single_step == state.STEP_STEPPED)) {
+        state.single_step = state.STEP_NONE;
+        enter_debug_mode(DCSR_CAUSE_STEP);
+      }
     }
     catch (trigger_matched_t& t)
     {