partially update spike to newer debug spec

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index a2e71a166702c40b4311e576bde229c1d211782c..7b42262c589a401a848945e08e77085741b4922b 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -2,6 +2,7 @@
 
 #include "processor.h"
 #include "mmu.h"
+#include "sim.h"
 #include <cassert>
 
 
@@ -43,25 +44,47 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 {
   commit_log_stash_privilege(p->get_state());
   reg_t npc = fetch.func(p, fetch.insn, pc);
-  if (npc != PC_SERIALIZE) {
+  if (!invalid_pc(npc)) {
     commit_log_print_insn(p->get_state(), pc, fetch.insn);
     p->update_histogram(pc);
   }
   return npc;
 }
 
+bool processor_t::slow_path()
+{
+  return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
+}
+
 // fetch/decode/execute loop
 void processor_t::step(size_t n)
 {
-  while (run && n > 0) {
+  if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+    // TODO: get_interrupt() isn't super fast. Does that matter?
+    if (sim->debug_module.get_interrupt(id)) {
+      enter_debug_mode(DCSR_CAUSE_DEBUGINT);
+    } else if (state.dcsr.halt) {
+      enter_debug_mode(DCSR_CAUSE_HALT);
+    }
+  } else {
+    // In Debug Mode, just do 11 steps at a time. Otherwise we're going to be
+    // spinning the rest of the time anyway.
+    n = std::min(n, (size_t) 11);
+  }
+
+  while (n > 0) {
     size_t instret = 0;
     reg_t pc = state.pc;
     mmu_t* _mmu = mmu;
 
     #define advance_pc() \
-     if (unlikely(pc == PC_SERIALIZE)) { \
+     if (unlikely(invalid_pc(pc))) { \
+       switch (pc) { \
+         case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
+         case PC_SERIALIZE_AFTER: instret++; break; \
+         default: abort(); \
+       } \
        pc = state.pc; \
-       state.serialized = true; \
        break; \
      } else { \
        state.pc = pc; \
@@ -70,18 +93,30 @@ void processor_t::step(size_t n)
 
     try
     {
-      check_timer();
       take_interrupt();
 
-      if (unlikely(debug))
+      if (unlikely(slow_path()))
       {
         while (instret < n)
         {
+          if (unlikely(state.single_step == state.STEP_STEPPING)) {
+            state.single_step = state.STEP_STEPPED;
+          }
+
           insn_fetch_t fetch = mmu->load_insn(pc);
-          if (!state.serialized)
+          if (debug && !state.serialized)
             disasm(fetch.insn);
           pc = execute_insn(this, pc, fetch);
+          bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
+
           advance_pc();
+
+          if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
+            state.single_step = state.STEP_NONE;
+            enter_debug_mode(DCSR_CAUSE_STEP);
+            // enter_debug_mode changed state.pc, so we can't just continue.
+            break;
+          }
         }
       }
       else while (instret < n)
@@ -117,6 +152,35 @@ miss:
     catch(trap_t& t)
     {
       take_trap(t, pc);
+      n = instret;
+    }
+    catch (trigger_matched_t& t)
+    {
+      if (mmu->matched_trigger) {
+        // This exception came from the MMU. That means the instruction hasn't
+        // fully executed yet. We start it again, but this time it won't throw
+        // an exception because matched_trigger is already set. (All memory
+        // instructions are idempotent so restarting is safe.)
+
+        insn_fetch_t fetch = mmu->load_insn(pc);
+        pc = execute_insn(this, pc, fetch);
+        advance_pc();
+
+        delete mmu->matched_trigger;
+        mmu->matched_trigger = NULL;
+      }
+      switch (state.mcontrol[t.index].action) {
+        case ACTION_DEBUG_MODE:
+          enter_debug_mode(DCSR_CAUSE_HWBP);
+          break;
+        case ACTION_DEBUG_EXCEPTION: {
+          mem_trap_t trap(CAUSE_BREAKPOINT, t.address);
+          take_trap(trap, pc);
+          break;
+        }
+        default:
+          abort();
+      }
     }
 
     state.minstret += instret;