WIP on priv spec v1.9

[riscv-isa-sim.git] / riscv / extension.cc

diff --git a/riscv/extension.cc b/riscv/extension.cc
index c2bea2e648635f30ef513a57d2b97ddcc46172b3..5321c42c17d96b5f7a985716f36691cc1215ecb2 100644 (file)
--- a/riscv/extension.cc
+++ b/riscv/extension.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "extension.h"
 #include "trap.h"
 
@@ -12,7 +14,13 @@ void extension_t::illegal_instruction()
 
 void extension_t::raise_interrupt()
 {
-  p->raise_interrupt(IRQ_COP);
+  reg_t prv = p->get_state()->prv;
+  reg_t mie = get_field(p->get_state()->mstatus, MSTATUS_MIE);
+
+  if (prv < PRV_M || (prv == PRV_M && mie))
+    p->raise_interrupt(IRQ_COP);
+
+  throw std::logic_error("a COP exception was posted, but interrupts are disabled!");
 }
 
 void extension_t::clear_interrupt()