//////////////////////////////////////// Utility Functions
+#undef DEBUG
+#ifdef DEBUG
+# define D(x) x
+#else
+# define D(x)
+#endif // DEBUG
+
void die(const char* msg)
{
fprintf(stderr, "gdbserver code died: %s\n", msg);
REG_FPR31 = 64,
REG_CSR0 = 65,
REG_CSR4095 = 4160,
- REG_END = 4161
+ REG_PRIV = 4161
};
//////////////////////////////////////// Functions to generate RISC-V opcodes.
// TODO: Does this already exist somewhere?
+#define ZERO 0
// Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
// spec says it should be 2 and 3.
#define S0 8
MATCH_SD;
}
+static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
+{
+#if 0
+ return (bits(offset, 11, 5) << 25) |
+ (bits(src, 4, 0) << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_SQ;
+#else
+ abort();
+#endif
+}
+
+static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
+{
+#if 0
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(rd, 4, 0) << 7) |
+ MATCH_LQ;
+#else
+ abort();
+#endif
+}
+
static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
{
return (bits(offset, 11, 0) << 20) |
MATCH_LB;
}
+static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
+{
+ return (bits(offset, 11, 5) << 25) |
+ (bits(src, 4, 0) << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_FSW;
+}
+
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
{
return (bits(offset, 11, 5) << 25) |
MATCH_FSD;
}
+static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
+{
+ return (bits(offset, 11, 5) << 25) |
+ (bits(src, 4, 0) << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_FLW;
+}
+
static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
{
return (bits(offset, 11, 5) << 25) |
MATCH_ORI;
}
+static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
+{
+ return (bits(imm, 11, 0) << 20) |
+ (src << 15) |
+ (dest << 7) |
+ MATCH_XORI;
+}
+
+static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
+{
+ return (bits(shamt, 4, 0) << 20) |
+ (src << 15) |
+ (dest << 7) |
+ MATCH_SRLI;
+}
+
+
static uint32_t nop()
{
return addi(0, 0, 0);
{
public:
halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
- operation_t(gdbserver), send_status(send_status) {};
+ operation_t(gdbserver), send_status(send_status),
+ state(ST_ENTER) {};
+
+ void write_dpc_program() {
+ gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
+ gs.dr_write32(1, csrr(S0, CSR_DPC));
+ gs.dr_write_store(2, S0, SLOT_DATA0);
+ gs.dr_write_jump(3);
+ gs.set_interrupt(0);
+ }
bool perform_step(unsigned int step) {
- switch (step) {
- case 0:
- // TODO: For now we just assume the target is 64-bit.
- gs.write_debug_ram(0, csrsi(CSR_DCSR, DCSR_HALT));
- gs.write_debug_ram(1, csrr(S0, CSR_DPC));
- gs.write_debug_ram(2, sd(S0, 0, (uint16_t) DEBUG_RAM_START));
- gs.write_debug_ram(3, csrr(S0, CSR_MSTATUS));
- gs.write_debug_ram(4, sd(S0, 0, (uint16_t) DEBUG_RAM_START + 8));
- gs.write_debug_ram(5, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*5))));
+ switch (state) {
+ gs.tselect_valid = false;
+ case ST_ENTER:
+ if (gs.xlen == 0) {
+ gs.dr_write32(0, xori(S1, ZERO, -1));
+ gs.dr_write32(1, srli(S1, S1, 31));
+ // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
+ gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
+ gs.dr_write32(3, srli(S1, S1, 31));
+ // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
+ gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
+ gs.dr_write_jump(5);
+ gs.set_interrupt(0);
+ state = ST_XLEN;
+
+ } else {
+ write_dpc_program();
+ state = ST_DPC;
+ }
+ return false;
+
+ case ST_XLEN:
+ {
+ uint32_t word0 = gs.dr_read32(0);
+ uint32_t word1 = gs.dr_read32(1);
+
+ if (word0 == 1 && word1 == 0) {
+ gs.xlen = 32;
+ } else if (word0 == 0xffffffff && word1 == 3) {
+ gs.xlen = 64;
+ } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
+ gs.xlen = 128;
+ }
+
+ write_dpc_program();
+ state = ST_DPC;
+ return false;
+ }
+
+ case ST_DPC:
+ gs.dpc = gs.dr_read(SLOT_DATA0);
+ gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
+ gs.dr_write_store(1, S0, SLOT_DATA0);
+ gs.dr_write_jump(2);
gs.set_interrupt(0);
- // We could read more registers here, but only on 64-bit targets. I'm
- // trying to keep The patterns here usable for 32-bit ISAs as well.
+ state = ST_MSTATUS;
return false;
- case 1:
- gs.dpc = ((uint64_t) gs.read_debug_ram(1) << 32) | gs.read_debug_ram(0);
- gs.mstatus = ((uint64_t) gs.read_debug_ram(3) << 32) | gs.read_debug_ram(2);
- gs.write_debug_ram(0, csrr(S0, CSR_DCSR));
- gs.write_debug_ram(1, sd(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*6))));
+ case ST_MSTATUS:
+ gs.mstatus = gs.dr_read(SLOT_DATA0);
+ gs.dr_write32(0, csrr(S0, CSR_DCSR));
+ gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write_jump(2);
gs.set_interrupt(0);
+ state = ST_DCSR;
return false;
- case 2:
- gs.dcsr = ((uint64_t) gs.read_debug_ram(5) << 32) | gs.read_debug_ram(4);
+ case ST_DCSR:
+ gs.dcsr = gs.dr_read32(4);
gs.sptbr_valid = false;
gs.pte_cache.clear();
break;
}
}
-
return true;
+
+ default:
+ assert(0);
}
- return false;
}
private:
bool send_status;
+ enum {
+ ST_ENTER,
+ ST_XLEN,
+ ST_DPC,
+ ST_MSTATUS,
+ ST_DCSR
+ } state;
};
class continue_op_t : public operation_t
operation_t(gdbserver), single_step(single_step) {};
bool perform_step(unsigned int step) {
+ D(fprintf(stderr, "continue step %d\n", step));
switch (step) {
case 0:
- gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START+16));
- gs.write_debug_ram(1, csrw(S0, CSR_DPC));
+ gs.dr_write_load(0, S0, SLOT_DATA0);
+ gs.dr_write32(1, csrw(S0, CSR_DPC));
+ // TODO: Isn't there a fence.i in Debug ROM already?
if (gs.fence_i_required) {
- gs.write_debug_ram(2, fence_i());
- gs.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
+ gs.dr_write32(2, fence_i());
+ gs.dr_write_jump(3);
gs.fence_i_required = false;
} else {
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write_jump(2);
}
- gs.write_debug_ram(4, gs.dpc);
- gs.write_debug_ram(5, gs.dpc >> 32);
+ gs.dr_write(SLOT_DATA0, gs.dpc);
gs.set_interrupt(0);
return false;
case 1:
- gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START+16));
- gs.write_debug_ram(1, csrw(S0, CSR_MSTATUS));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
- gs.write_debug_ram(4, gs.mstatus);
- gs.write_debug_ram(5, gs.mstatus >> 32);
+ gs.dr_write_load(0, S0, SLOT_DATA0);
+ gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
+ gs.dr_write_jump(2);
+ gs.dr_write(SLOT_DATA0, gs.mstatus);
gs.set_interrupt(0);
return false;
case 2:
- gs.write_debug_ram(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
- gs.write_debug_ram(1, csrw(S0, CSR_DCSR));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
+ gs.dr_write32(1, csrw(S0, CSR_DCSR));
+ gs.dr_write_jump(2);
reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
dcsr = set_field(dcsr, DCSR_STEP, single_step);
dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
- gs.write_debug_ram(4, dcsr);
+ gs.dr_write32(4, dcsr);
gs.set_interrupt(0);
return true;
bool perform_step(unsigned int step)
{
+ D(fprintf(stderr, "register_read step %d\n", step));
if (step == 0) {
gs.start_packet();
// x0 is always zero.
- gs.send((reg_t) 0);
+ if (gs.xlen == 32) {
+ gs.send((uint32_t) 0);
+ } else {
+ gs.send((uint64_t) 0);
+ }
- gs.write_debug_ram(0, sd(1, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(1, sd(2, 0, (uint16_t) DEBUG_RAM_START + 0));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write_store(0, 1, SLOT_DATA0);
+ gs.dr_write_store(1, 2, SLOT_DATA1);
+ gs.dr_write_jump(2);
gs.set_interrupt(0);
return false;
}
- gs.send(((uint64_t) gs.read_debug_ram(5) << 32) | gs.read_debug_ram(4));
+ if (gs.xlen == 32) {
+ gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
+ } else {
+ gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
+ }
if (step >= 16) {
gs.end_packet();
return true;
}
- gs.send(((uint64_t) gs.read_debug_ram(1) << 32) | gs.read_debug_ram(0));
+ if (gs.xlen == 32) {
+ gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
+ } else {
+ gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
+ }
unsigned int current_reg = 2 * step + 1;
unsigned int i = 0;
if (current_reg == S1) {
- gs.write_debug_ram(i++, ld(S1, 0, (uint16_t) DEBUG_RAM_END - 8));
+ gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
}
- gs.write_debug_ram(i++, sd(current_reg, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write_store(i++, current_reg, SLOT_DATA0);
if (current_reg + 1 == S0) {
- gs.write_debug_ram(i++, csrr(S0, CSR_DSCRATCH));
+ gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
+ }
+ if (step < 15) {
+ gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
}
- gs.write_debug_ram(i++, sd(current_reg+1, 0, (uint16_t) DEBUG_RAM_START + 0));
- gs.write_debug_ram(i, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*i))));
+ gs.dr_write_jump(i);
gs.set_interrupt(0);
return false;
// send(p->state.XPR[reg - REG_XPR0]);
} else if (reg == REG_PC) {
gs.start_packet();
- gs.send(gs.dpc);
+ if (gs.xlen == 32) {
+ gs.send((uint32_t) gs.dpc);
+ } else {
+ gs.send(gs.dpc);
+ }
gs.end_packet();
return true;
} else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
// send(p->state.FPR[reg - REG_FPR0]);
- gs.write_debug_ram(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(1, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*1))));
+ if (gs.xlen == 32) {
+ gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ } else {
+ gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ }
+ gs.dr_write_jump(1);
} else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
- gs.write_debug_ram(0, csrr(S0, reg - REG_CSR0));
- gs.write_debug_ram(1, sd(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
+ gs.dr_write_store(1, S0, SLOT_DATA0);
+ gs.dr_write_jump(2);
// If we hit an exception reading the CSR, we'll end up returning ~0 as
// the register's value, which is what we want. (Right?)
- gs.write_debug_ram(4, 0xffffffff);
- gs.write_debug_ram(5, 0xffffffff);
+ gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
+ } else if (reg == REG_PRIV) {
+ gs.start_packet();
+ gs.send((uint8_t) get_field(gs.dcsr, DCSR_PRV));
+ gs.end_packet();
+ return true;
} else {
gs.send_packet("E02");
return true;
case 1:
gs.start_packet();
- gs.send(((uint64_t) gs.read_debug_ram(5) << 32) | gs.read_debug_ram(4));
+ if (gs.xlen == 32) {
+ gs.send(gs.dr_read32(4));
+ } else {
+ gs.send(gs.dr_read(SLOT_DATA0));
+ }
gs.end_packet();
return true;
}
bool perform_step(unsigned int step)
{
- gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(4, value);
- gs.write_debug_ram(5, value >> 32);
+ gs.dr_write_load(0, S0, SLOT_DATA0);
+ gs.dr_write(SLOT_DATA0, value);
if (reg == S0) {
- gs.write_debug_ram(1, csrw(S0, CSR_DSCRATCH));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
+ gs.dr_write_jump(2);
} else if (reg == S1) {
- gs.write_debug_ram(1, sd(S0, 0, (uint16_t) DEBUG_RAM_END - 8));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write_store(1, S0, SLOT_DATA_LAST);
+ gs.dr_write_jump(2);
} else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
- gs.write_debug_ram(1, addi(reg, S0, 0));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write32(1, addi(reg, S0, 0));
+ gs.dr_write_jump(2);
} else if (reg == REG_PC) {
gs.dpc = value;
return true;
} else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
- // send(p->state.FPR[reg - REG_FPR0]);
- gs.write_debug_ram(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(1, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*1))));
+ if (gs.xlen == 32) {
+ gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ } else {
+ gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ }
+ gs.dr_write_jump(1);
} else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
- gs.write_debug_ram(1, csrw(S0, reg - REG_CSR0));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
+ gs.dr_write_jump(2);
if (reg == REG_CSR0 + CSR_SPTBR) {
gs.sptbr = value;
gs.sptbr_valid = true;
}
+ } else if (reg == REG_PRIV) {
+ gs.dcsr = set_field(gs.dcsr, DCSR_PRV, value);
+ return true;
} else {
gs.send_packet("E02");
return true;
if (step == 0) {
// address goes in S0
paddr = gs.translate(vaddr);
- access_size = (paddr % length);
- if (access_size == 0)
- access_size = length;
- if (access_size > 8)
- access_size = 8;
+ access_size = gs.find_access_size(paddr, length);
- gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write_load(0, S0, SLOT_DATA0);
switch (access_size) {
case 1:
- gs.write_debug_ram(1, lb(S1, S0, 0));
+ gs.dr_write32(1, lb(S1, S0, 0));
break;
case 2:
- gs.write_debug_ram(1, lh(S1, S0, 0));
+ gs.dr_write32(1, lh(S1, S0, 0));
break;
case 4:
- gs.write_debug_ram(1, lw(S1, S0, 0));
+ gs.dr_write32(1, lw(S1, S0, 0));
break;
case 8:
- gs.write_debug_ram(1, ld(S1, S0, 0));
+ gs.dr_write32(1, ld(S1, S0, 0));
break;
}
- gs.write_debug_ram(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
- gs.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
- gs.write_debug_ram(4, paddr);
- gs.write_debug_ram(5, paddr >> 32);
+ gs.dr_write_store(2, S1, SLOT_DATA1);
+ gs.dr_write_jump(3);
+ gs.dr_write(SLOT_DATA0, paddr);
gs.set_interrupt(0);
if (!data) {
}
char buffer[3];
- reg_t value = ((uint64_t) gs.read_debug_ram(7) << 32) | gs.read_debug_ram(6);
+ reg_t value = gs.dr_read(SLOT_DATA1);
for (unsigned int i = 0; i < access_size; i++) {
if (data) {
*(data++) = value & 0xff;
- fprintf(stderr, "%02x", (unsigned int) (value & 0xff));
+ D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
} else {
sprintf(buffer, "%02x", (unsigned int) (value & 0xff));
gs.send(buffer);
}
value >>= 8;
}
- if (data)
- fprintf(stderr, "\n");
+ if (data) {
+ D(fprintf(stderr, "\n"));
+ }
length -= access_size;
paddr += access_size;
}
return true;
} else {
- gs.write_debug_ram(4, paddr);
- gs.write_debug_ram(5, paddr >> 32);
+ gs.dr_write(SLOT_DATA0, paddr);
gs.set_interrupt(0);
return false;
}
bool perform_step(unsigned int step)
{
reg_t paddr = gs.translate(vaddr);
+
+ unsigned int data_offset;
+ switch (gs.xlen) {
+ case 32:
+ data_offset = slot_offset32[SLOT_DATA1];
+ break;
+ case 64:
+ data_offset = slot_offset64[SLOT_DATA1];
+ break;
+ case 128:
+ data_offset = slot_offset128[SLOT_DATA1];
+ break;
+ default:
+ abort();
+ }
+
if (step == 0) {
+ access_size = gs.find_access_size(paddr, length);
+
+ D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
+ access_size));
+ for (unsigned int i = 0; i < length; i++) {
+ D(fprintf(stderr, "%02x", data[i]));
+ }
+ D(fprintf(stderr, "\n"));
+
// address goes in S0
- access_size = (paddr % length);
- if (access_size == 0)
- access_size = length;
- if (access_size > 8)
- access_size = 8;
-
- fprintf(stderr, "write to 0x%lx -> 0x%lx: ", vaddr, paddr);
- for (unsigned int i = 0; i < length; i++)
- fprintf(stderr, "%02x", data[i]);
- fprintf(stderr, "\n");
-
- gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write_load(0, S0, SLOT_DATA0);
switch (access_size) {
case 1:
- gs.write_debug_ram(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
- gs.write_debug_ram(2, sb(S1, S0, 0));
- gs.write_debug_ram(6, data[0]);
+ gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
+ gs.dr_write32(2, sb(S1, S0, 0));
+ gs.dr_write32(data_offset, data[0]);
break;
case 2:
- gs.write_debug_ram(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
- gs.write_debug_ram(2, sh(S1, S0, 0));
- gs.write_debug_ram(6, data[0] | (data[1] << 8));
+ gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
+ gs.dr_write32(2, sh(S1, S0, 0));
+ gs.dr_write32(data_offset, data[0] | (data[1] << 8));
break;
case 4:
- gs.write_debug_ram(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
- gs.write_debug_ram(2, sw(S1, S0, 0));
- gs.write_debug_ram(6, data[0] | (data[1] << 8) |
+ gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
+ gs.dr_write32(2, sw(S1, S0, 0));
+ gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
(data[2] << 16) | (data[3] << 24));
break;
case 8:
- gs.write_debug_ram(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
- gs.write_debug_ram(2, sd(S1, S0, 0));
- gs.write_debug_ram(6, data[0] | (data[1] << 8) |
+ gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
+ gs.dr_write32(2, sd(S1, S0, 0));
+ gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
(data[2] << 16) | (data[3] << 24));
- gs.write_debug_ram(7, data[4] | (data[5] << 8) |
+ gs.dr_write32(data_offset+1, data[4] | (data[5] << 8) |
(data[6] << 16) | (data[7] << 24));
break;
default:
+ fprintf(stderr, "gdbserver error: write %d bytes to 0x%lx -> 0x%lx; "
+ "access_size=%d\n", length, vaddr, paddr, access_size);
gs.send_packet("E12");
return true;
}
- gs.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
- gs.write_debug_ram(4, paddr);
- gs.write_debug_ram(5, paddr >> 32);
+ gs.dr_write_jump(3);
+ gs.dr_write(SLOT_DATA0, paddr);
gs.set_interrupt(0);
return false;
}
- if (gs.read_debug_ram(DEBUG_RAM_SIZE / 4 - 1)) {
+ if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
fprintf(stderr, "Exception happened while writing to 0x%lx -> 0x%lx\n",
vaddr, paddr);
}
const unsigned char *d = data + offset;
switch (access_size) {
case 1:
- gs.write_debug_ram(6, d[0]);
+ gs.dr_write32(data_offset, d[0]);
break;
case 2:
- gs.write_debug_ram(6, d[0] | (d[1] << 8));
+ gs.dr_write32(data_offset, d[0] | (d[1] << 8));
break;
case 4:
- gs.write_debug_ram(6, d[0] | (d[1] << 8) |
+ gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
(d[2] << 16) | (d[3] << 24));
break;
case 8:
- gs.write_debug_ram(6, d[0] | (d[1] << 8) |
+ gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
(d[2] << 16) | (d[3] << 24));
- gs.write_debug_ram(7, d[4] | (d[5] << 8) |
+ gs.dr_write32(data_offset+1, d[4] | (d[5] << 8) |
(d[6] << 16) | (d[7] << 24));
break;
default:
- gs.send_packet("E12");
+ gs.send_packet("E13");
return true;
}
- gs.write_debug_ram(4, paddr + offset);
- gs.write_debug_ram(5, (paddr + offset) >> 32);
+ gs.dr_write(SLOT_DATA0, paddr + offset);
gs.set_interrupt(0);
return false;
}
case STATE_START:
break;
case STATE_READ_SPTBR:
- gs.sptbr = ((uint64_t) gs.read_debug_ram(5) << 32) | gs.read_debug_ram(4);
+ gs.sptbr = gs.dr_read(SLOT_DATA0);
gs.sptbr_valid = true;
break;
case STATE_READ_PTE:
- gs.pte_cache[pte_addr] = ((uint64_t) gs.read_debug_ram(5) << 32) |
- gs.read_debug_ram(4);
- fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]);
+ if (ptesize == 4) {
+ gs.pte_cache[pte_addr] = gs.dr_read32(4);
+ } else {
+ gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
+ gs.dr_read32(4);
+ }
+ D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
break;
}
if (!gs.sptbr_valid) {
state = STATE_READ_SPTBR;
- gs.write_debug_ram(0, csrr(S0, CSR_SPTBR));
- gs.write_debug_ram(1, sd(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+ gs.dr_write32(0, csrr(S0, CSR_SPTBR));
+ gs.dr_write_store(1, S0, SLOT_DATA0);
+ gs.dr_write_jump(2);
gs.set_interrupt(0);
return false;
}
if (it == gs.pte_cache.end()) {
state = STATE_READ_PTE;
if (ptesize == 4) {
- gs.write_debug_ram(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(1, lw(S1, S0, 0));
- gs.write_debug_ram(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(1, lw(S1, S0, 0));
+ gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
} else {
- gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
- gs.write_debug_ram(1, ld(S1, S0, 0));
- gs.write_debug_ram(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
+ assert(gs.xlen >= 64);
+ gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(1, ld(S1, S0, 0));
+ gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
}
- gs.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
- gs.write_debug_ram(4, pte_addr);
- gs.write_debug_ram(5, pte_addr >> 32);
+ gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
+ gs.dr_write32(4, pte_addr);
+ gs.dr_write32(5, pte_addr >> 32);
gs.set_interrupt(0);
return false;
}
reg_t pte_addr;
};
+class hardware_breakpoint_insert_op_t : public operation_t
+{
+ public:
+ hardware_breakpoint_insert_op_t(gdbserver_t& gdbserver,
+ hardware_breakpoint_t bp) :
+ operation_t(gdbserver), state(STATE_START), bp(bp) {};
+
+ void write_new_index_program()
+ {
+ gs.dr_write_load(0, S0, SLOT_DATA1);
+ gs.dr_write32(1, csrw(S0, CSR_TSELECT));
+ gs.dr_write32(2, csrr(S0, CSR_TSELECT));
+ gs.dr_write_store(3, S0, SLOT_DATA1);
+ gs.dr_write_jump(4);
+ gs.dr_write(SLOT_DATA1, bp.index);
+ }
+
+ bool perform_step(unsigned int step)
+ {
+ switch (state) {
+ case STATE_START:
+ bp.index = 0;
+ write_new_index_program();
+ state = STATE_CHECK_INDEX;
+ break;
+
+ case STATE_CHECK_INDEX:
+ if (gs.dr_read(SLOT_DATA1) != bp.index) {
+ // We've exhausted breakpoints without finding an appropriate one.
+ gs.send_packet("E58");
+ return true;
+ }
+
+ gs.dr_write32(0, csrr(S0, CSR_TDATA1));
+ gs.dr_write_store(1, S0, SLOT_DATA0);
+ gs.dr_write_jump(2);
+ state = STATE_CHECK_MCONTROL;
+ break;
+
+ case STATE_CHECK_MCONTROL:
+ {
+ reg_t mcontrol = gs.dr_read(SLOT_DATA0);
+ unsigned int type = mcontrol >> (gs.xlen - 4);
+ if (type == 0) {
+ // We've exhausted breakpoints without finding an appropriate one.
+ gs.send_packet("E58");
+ return true;
+ }
+
+ if (type == 2 &&
+ !get_field(mcontrol, MCONTROL_EXECUTE) &&
+ !get_field(mcontrol, MCONTROL_LOAD) &&
+ !get_field(mcontrol, MCONTROL_STORE)) {
+ // Found an unused trigger.
+ gs.dr_write_load(0, S0, SLOT_DATA1);
+ gs.dr_write32(1, csrw(S0, CSR_TDATA1));
+ gs.dr_write_jump(2);
+ mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE);
+ mcontrol = set_field(mcontrol, MCONTROL_DMODE(gs.xlen), 1);
+ mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
+ mcontrol = set_field(mcontrol, MCONTROL_M, 1);
+ mcontrol = set_field(mcontrol, MCONTROL_H, 1);
+ mcontrol = set_field(mcontrol, MCONTROL_S, 1);
+ mcontrol = set_field(mcontrol, MCONTROL_U, 1);
+ mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
+ mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
+ mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
+ // For store triggers it's nicer to fire just before the
+ // instruction than just after. However, gdb doesn't clear the
+ // breakpoints and step before resuming from a store trigger.
+ // That means that without extra code, you'll keep hitting the
+ // same watchpoint over and over again. That's not useful at all.
+ // Instead of fixing this the right way, just set timing=1 for
+ // those triggers.
+ if (bp.load || bp.store)
+ mcontrol = set_field(mcontrol, MCONTROL_TIMING, 1);
+
+ gs.dr_write(SLOT_DATA1, mcontrol);
+ state = STATE_WRITE_ADDRESS;
+ } else {
+ bp.index++;
+ write_new_index_program();
+ state = STATE_CHECK_INDEX;
+ }
+ }
+ break;
+
+ case STATE_WRITE_ADDRESS:
+ {
+ gs.dr_write_load(0, S0, SLOT_DATA1);
+ gs.dr_write32(1, csrw(S0, CSR_TDATA2));
+ gs.dr_write_jump(2);
+ gs.dr_write(SLOT_DATA1, bp.vaddr);
+ gs.set_interrupt(0);
+ gs.send_packet("OK");
+
+ gs.hardware_breakpoints.insert(bp);
+
+ return true;
+ }
+ }
+
+ gs.set_interrupt(0);
+ return false;
+ }
+
+ private:
+ enum {
+ STATE_START,
+ STATE_CHECK_INDEX,
+ STATE_CHECK_MCONTROL,
+ STATE_WRITE_ADDRESS
+ } state;
+ hardware_breakpoint_t bp;
+};
+
+class maybe_save_tselect_op_t : public operation_t
+{
+ public:
+ maybe_save_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
+ bool perform_step(unsigned int step) {
+ if (gs.tselect_valid)
+ return true;
+
+ switch (step) {
+ case 0:
+ gs.dr_write32(0, csrr(S0, CSR_TDATA1));
+ gs.dr_write_store(1, S0, SLOT_DATA0);
+ gs.dr_write_jump(2);
+ gs.set_interrupt(0);
+ return false;
+ case 1:
+ gs.tselect = gs.dr_read(SLOT_DATA0);
+ gs.tselect_valid = true;
+ break;
+ }
+ return true;
+ }
+};
+
+class maybe_restore_tselect_op_t : public operation_t
+{
+ public:
+ maybe_restore_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
+ bool perform_step(unsigned int step) {
+ if (gs.tselect_valid) {
+ gs.dr_write_load(0, S0, SLOT_DATA1);
+ gs.dr_write32(1, csrw(S0, CSR_TSELECT));
+ gs.dr_write_jump(2);
+ gs.dr_write(SLOT_DATA1, gs.tselect);
+ }
+ return true;
+ }
+};
+
+class hardware_breakpoint_remove_op_t : public operation_t
+{
+ public:
+ hardware_breakpoint_remove_op_t(gdbserver_t& gdbserver,
+ hardware_breakpoint_t bp) :
+ operation_t(gdbserver), bp(bp) {};
+
+ bool perform_step(unsigned int step) {
+ gs.dr_write32(0, addi(S0, ZERO, bp.index));
+ gs.dr_write32(1, csrw(S0, CSR_TSELECT));
+ gs.dr_write32(2, csrw(ZERO, CSR_TDATA1));
+ gs.dr_write_jump(3);
+ gs.set_interrupt(0);
+ return true;
+ }
+
+ private:
+ hardware_breakpoint_t bp;
+};
+
////////////////////////////// gdbserver itself
gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
+ xlen(0),
sim(sim),
client_fd(0),
recv_buf(64 * 1024), send_buf(64 * 1024)
}
}
+unsigned int gdbserver_t::find_access_size(reg_t address, int length)
+{
+ reg_t composite = address | length;
+ if ((composite & 0x7) == 0 && xlen >= 64)
+ return 8;
+ if ((composite & 0x3) == 0)
+ return 4;
+ return 1;
+}
+
reg_t gdbserver_t::translate(reg_t vaddr)
{
unsigned int vm = virtual_memory();
reg_t vpn = vaddr >> PGSHIFT;
reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
paddr += vaddr & (PGSIZE-1);
- fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr);
+ D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
return paddr;
}
}
return get_field(mstatus, MSTATUS_VM);
}
-void gdbserver_t::write_debug_ram(unsigned int index, uint32_t value)
+void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
{
sim->debug_module.ram_write32(index, value);
}
-uint32_t gdbserver_t::read_debug_ram(unsigned int index)
+void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
+{
+ dr_write32(index, value);
+ dr_write32(index+1, value >> 32);
+}
+
+void gdbserver_t::dr_write(enum slot slot, uint64_t value)
+{
+ switch (xlen) {
+ case 32:
+ dr_write32(slot_offset32[slot], value);
+ break;
+ case 64:
+ dr_write64(slot_offset64[slot], value);
+ break;
+ case 128:
+ default:
+ abort();
+ }
+}
+
+void gdbserver_t::dr_write_jump(unsigned int index)
+{
+ dr_write32(index, jal(0,
+ (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
+}
+
+void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
+{
+ assert(slot != SLOT_INST0 || index > 2);
+ assert(slot != SLOT_DATA0 || index < 4 || index > 6);
+ assert(slot != SLOT_DATA1 || index < 5 || index > 10);
+ assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
+ switch (xlen) {
+ case 32:
+ return dr_write32(index,
+ sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
+ case 64:
+ return dr_write32(index,
+ sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
+ case 128:
+ return dr_write32(index,
+ sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
+ default:
+ fprintf(stderr, "xlen is %d!\n", xlen);
+ abort();
+ }
+}
+
+void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
+{
+ switch (xlen) {
+ case 32:
+ return dr_write32(index,
+ lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
+ case 64:
+ return dr_write32(index,
+ ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
+ case 128:
+ return dr_write32(index,
+ lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
+ default:
+ fprintf(stderr, "xlen is %d!\n", xlen);
+ abort();
+ }
+}
+
+uint32_t gdbserver_t::dr_read32(unsigned int index)
+{
+ uint32_t value = sim->debug_module.ram_read32(index);
+ D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
+ return value;
+}
+
+uint64_t gdbserver_t::dr_read64(unsigned int index)
{
- return sim->debug_module.ram_read32(index);
+ return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
+}
+
+uint64_t gdbserver_t::dr_read(enum slot slot)
+{
+ switch (xlen) {
+ case 32:
+ return dr_read32(slot_offset32[slot]);
+ case 64:
+ return dr_read64(slot_offset64[slot]);
+ case 128:
+ abort();
+ default:
+ abort();
+ }
}
void gdbserver_t::add_operation(operation_t* operation)
// Client can't take any more data right now.
break;
} else {
- fprintf(stderr, "wrote %ld bytes: ", bytes);
+ D(fprintf(stderr, "wrote %ld bytes: ", bytes));
for (unsigned int i = 0; i < bytes; i++) {
- fprintf(stderr, "%c", send_buf[i]);
+ D(fprintf(stderr, "%c", send_buf[i]));
}
- fprintf(stderr, "\n");
+ D(fprintf(stderr, "\n"));
send_buf.consume(bytes);
}
}
}
if (packet.empty() && b == 3) {
- fprintf(stderr, "Received interrupt\n");
+ D(fprintf(stderr, "Received interrupt\n"));
recv_buf.consume(1);
handle_interrupt();
break;
return send_packet("E30");
}
+ add_operation(new maybe_restore_tselect_op_t(*this));
add_operation(new continue_op_t(*this, false));
}
return send_packet("E40");
}
+ add_operation(new maybe_restore_tselect_op_t(*this));
add_operation(new continue_op_t(*this, true));
}
extended_mode = true;
}
+void gdbserver_t::software_breakpoint_insert(reg_t vaddr, unsigned int size)
+{
+ fence_i_required = true;
+ add_operation(new collect_translation_info_op_t(*this, vaddr, size));
+ unsigned char* inst = new unsigned char[4];
+ if (size == 2) {
+ inst[0] = C_EBREAK & 0xff;
+ inst[1] = (C_EBREAK >> 8) & 0xff;
+ } else {
+ inst[0] = EBREAK & 0xff;
+ inst[1] = (EBREAK >> 8) & 0xff;
+ inst[2] = (EBREAK >> 16) & 0xff;
+ inst[3] = (EBREAK >> 24) & 0xff;
+ }
+
+ software_breakpoint_t bp = {
+ .vaddr = vaddr,
+ .size = size
+ };
+ software_breakpoints[vaddr] = bp;
+ add_operation(new memory_read_op_t(*this, bp.vaddr, bp.size,
+ software_breakpoints[bp.vaddr].instruction));
+ add_operation(new memory_write_op_t(*this, bp.vaddr, bp.size, inst));
+}
+
+void gdbserver_t::software_breakpoint_remove(reg_t vaddr, unsigned int size)
+{
+ fence_i_required = true;
+ add_operation(new collect_translation_info_op_t(*this, vaddr, size));
+
+ software_breakpoint_t found_bp = software_breakpoints[vaddr];
+ unsigned char* instruction = new unsigned char[4];
+ memcpy(instruction, found_bp.instruction, 4);
+ add_operation(new memory_write_op_t(*this, found_bp.vaddr,
+ found_bp.size, instruction));
+ software_breakpoints.erase(vaddr);
+}
+
+void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t &bp)
+{
+ add_operation(new maybe_save_tselect_op_t(*this));
+ add_operation(new hardware_breakpoint_insert_op_t(*this, bp));
+}
+
+void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t &bp)
+{
+ add_operation(new maybe_save_tselect_op_t(*this));
+ hardware_breakpoint_t found = *hardware_breakpoints.find(bp);
+ add_operation(new hardware_breakpoint_remove_op_t(*this, found));
+}
+
void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
{
- // insert: Z type,addr,kind
- // remove: z type,addr,kind
+ // insert: Z type,addr,length
+ // remove: z type,addr,length
+
+ // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
+ // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
+ // length is in bytes. For a software breakpoint, length specifies the size
+ // of the instruction to be patched. For hardware breakpoints and watchpoints
+ // length specifies the memory region to be monitored. To avoid potential
+ // problems with duplicate packets, the operations should be implemented in
+ // an idempotent way.
- software_breakpoint_t bp;
bool insert = (packet[1] == 'Z');
std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
- int type = consume_hex_number(iter, packet.end());
+ gdb_breakpoint_type_t type = static_cast<gdb_breakpoint_type_t>(
+ consume_hex_number(iter, packet.end()));
if (*iter != ',')
return send_packet("E50");
iter++;
- bp.address = consume_hex_number(iter, packet.end());
+ reg_t address = consume_hex_number(iter, packet.end());
if (*iter != ',')
return send_packet("E51");
iter++;
- bp.size = consume_hex_number(iter, packet.end());
+ unsigned int size = consume_hex_number(iter, packet.end());
// There may be more options after a ; here, but we don't support that.
if (*iter != '#')
return send_packet("E52");
- if (bp.size != 2 && bp.size != 4) {
- return send_packet("E53");
- }
-
- fence_i_required = true;
- add_operation(new collect_translation_info_op_t(*this, bp.address, bp.size));
- if (insert) {
- unsigned char* swbp = new unsigned char[4];
- if (bp.size == 2) {
- swbp[0] = C_EBREAK & 0xff;
- swbp[1] = (C_EBREAK >> 8) & 0xff;
- } else {
- swbp[0] = EBREAK & 0xff;
- swbp[1] = (EBREAK >> 8) & 0xff;
- swbp[2] = (EBREAK >> 16) & 0xff;
- swbp[3] = (EBREAK >> 24) & 0xff;
- }
+ switch (type) {
+ case GB_SOFTWARE:
+ if (size != 2 && size != 4) {
+ return send_packet("E53");
+ }
+ if (insert) {
+ software_breakpoint_insert(address, size);
+ } else {
+ software_breakpoint_remove(address, size);
+ }
+ break;
- breakpoints[bp.address] = new software_breakpoint_t(bp);
- add_operation(new memory_read_op_t(*this, bp.address, bp.size,
- breakpoints[bp.address]->instruction));
- add_operation(new memory_write_op_t(*this, bp.address, bp.size, swbp));
+ case GB_HARDWARE:
+ case GB_WRITE:
+ case GB_READ:
+ case GB_ACCESS:
+ {
+ hardware_breakpoint_t bp = {
+ .vaddr = address,
+ .size = size
+ };
+ bp.load = (type == GB_READ || type == GB_ACCESS);
+ bp.store = (type == GB_WRITE || type == GB_ACCESS);
+ bp.execute = (type == GB_HARDWARE || type == GB_ACCESS);
+ if (insert) {
+ hardware_breakpoint_insert(bp);
+ // Insert might fail if there's no space, so the insert operation will
+ // send its own OK (or not).
+ return;
+ } else {
+ hardware_breakpoint_remove(bp);
+ }
+ }
+ break;
- } else {
- software_breakpoint_t *found_bp;
- found_bp = breakpoints[bp.address];
- unsigned char* instruction = new unsigned char[4];
- memcpy(instruction, found_bp->instruction, 4);
- add_operation(new memory_write_op_t(*this, found_bp->address,
- found_bp->size, instruction));
- breakpoints.erase(bp.address);
- delete found_bp;
+ default:
+ return send_packet("E56");
}
return send_packet("OK");
send("swbreak+;");
}
}
+ send("PacketSize=131072;");
return end_packet();
}
- fprintf(stderr, "Unsupported query %s\n", name.c_str());
+ D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
return send_packet("");
}
return;
}
- fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size());
- print_packet(packet);
+ D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
+ D(print_packet(packet));
send("+");
switch (packet[1]) {
}
// Not supported.
- fprintf(stderr, "** Unsupported packet: ");
- print_packet(packet);
+ D(fprintf(stderr, "** Unsupported packet: "));
+ D(print_packet(packet));
send_packet("");
}
}
}
+void gdbserver_t::send(uint8_t value)
+{
+ char buffer[3];
+ sprintf(buffer, "%02x", (int) value);
+ send(buffer);
+}
+
void gdbserver_t::send_packet(const char* data)
{
start_packet();
projects / riscv-isa-sim.git / blobdiff