Generate instruction decoder dynamically

[riscv-isa-sim.git] / riscv / htif.h

diff --git a/riscv/htif.h b/riscv/htif.h
index 0d8d1b7087d2cab688693ae4135761601a57316b..3e4a88dc6a1ca1af495221ea075c4169bcff2887 100644 (file)
--- a/riscv/htif.h
+++ b/riscv/htif.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _HTIF_H
 #define _HTIF_H
 
@@ -16,7 +18,7 @@ class htif_isasim_t : public htif_pthread_t
 public:
   htif_isasim_t(sim_t* _sim, const std::vector<std::string>& args);
   void tick();
-  void stop();
+  bool done();
 
 private:
   sim_t* sim;