Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / add.h

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index bfbc48568ddbf707f67c57f718022f31b370199c..895e2b1867dbf29aee59a86fc68fcbad5e2535f1 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1 @@
-RC = sext32(RA + RB);
-
+WRITE_RD(sext_xlen(RS1 + RS2));