[sim,xcc] Changed instruction format to RISC-V

[riscv-isa-sim.git] / riscv / insns / addi.h

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index c84299d2585cf481467922f57b63b9178c736f5d..6935ccadea8c0c76ce4f2cdff22232ef7e1631ae 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RT = sext32(RS + SIMM);
+RA = sext32(SIMM + RB);