Instructions are no longer member functions

[riscv-isa-sim.git] / riscv / insns / amoand_w.h

diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 18a92494856d83f4f846b514d6338fb74b936db7..91866dcfef7d3f46ba994c5265063c8bd279f369 100644 (file)
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 & v);
+reg_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, RS2 & v);
 RD = v;