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[riscv-isa-sim.git] / riscv / insns / amoand_w.h

diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 32ea7f70fa9a643c598e663898b655c8269011cd..f7e1ba7c06262b785db4d20ae7a32ab2220f3bb6 100644 (file)
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,2 @@
-reg_t v = MMU.load_int32(RS1);
-MMU.store_uint32(RS1, RS2 & v);
-WRITE_RD(v);
+require_extension('A');
+WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; })));