[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amow_max.h

diff --git a/riscv/insns/amow_max.h b/riscv/insns/amow_max.h
index c5318e789e54db8cd0b29b8211a549186572c813..c4854d1662139dd5338919a49c6bc85dd37033e2 100644 (file)
--- a/riscv/insns/amow_max.h
+++ b/riscv/insns/amow_max.h
@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::max(int32_t(RA),v));
-RC = v;
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
+RDR = v;