[sim,xcc] Changed instruction format to RISC-V

[riscv-isa-sim.git] / riscv / insns / andi.h

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 669b65891e77e20d7ad3e6ebbcceef7ec16c8d45..86a045c2ff0b54da48954d0a415f41b17237fb76 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RT = RS & IMM;
+RA = IMM & RB;