Use simpler MTVEC scheme

[riscv-isa-sim.git] / riscv / insns / andi.h

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 2c90b8bd2844b439ed50c6efda23e39328609cc5..bcc51e44071ab6bdff0ac53fd81bf3d1acf0764d 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RDI = SIMM & RS1;
+WRITE_RD(insn.i_imm() & RS1);