Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / bltu.h

diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index 186dcbef5c4669d405db435b9df1d6f313274be6..ff75e8a6da36a1e7b6f662685499b53aaf7b997f 100644 (file)
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) < cmp_trunc(RS2))
-  npc = BRANCH_TARGET;
+if(RS1 < RS2)
+  set_pc(BRANCH_TARGET);