clean up shift instruction implementation

[riscv-isa-sim.git] / riscv / insns / c_addiw.h

diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
index ae4980edce24b3bf7650c2ba34a8bd1aedb46c42..05d349713fed39ddd5c4b2356944d8b92f7624e5 100644 (file)
--- a/riscv/insns/c_addiw.h
+++ b/riscv/insns/c_addiw.h
@@ -1,7 +1,3 @@
 require_extension('C');
-if (xlen == 32) {
-  WRITE_RD(RVC_RS1 & insn.rvc_imm()); // c.andi
-} else {
-  require(insn.rvc_rd() != 0);
-  WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));
-}
+require_rv64;
+WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));