Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_flwsp.h

diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h
new file mode 100644 (file)
index 0000000..2d2dd5c
--- /dev/null
+++ b/riscv/insns/c_flwsp.h
@@ -0,0 +1,9 @@
+require_extension('C');
+if (xlen == 32) {
+  require_extension('F');
+  require_fp;
+  WRITE_FRD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
+} else {
+  require(insn.rvc_rd() != 0);
+  WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
+}