Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / c_li.h

diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
index e65614ed6d022cb398ea0209980b3ee0dc1edc50..f9fd66b2f32ee651f97a76c89ba68da0bce1cc56 100644 (file)
--- a/riscv/insns/c_li.h
+++ b/riscv/insns/c_li.h
@@ -1,2 +1,2 @@
-require_rvc;
-CRD = CIMM6;
+require_extension('C');
+WRITE_RD(insn.rvc_imm());