Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"

[riscv-isa-sim.git] / riscv / insns / c_lwsp.h

diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index 8d9b9e3bf845326187998905ab39c11db1597bb3..b3d74dbf087fb09553ca438bf4c44629ecfdc032 100644 (file)
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,2 +1,3 @@
-require_rvc;
+require_extension('C');
+require(insn.rvc_rd() != 0);
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));