Add rest of RV32C instructions

[riscv-isa-sim.git] / riscv / insns / c_sdsp.h

diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
index ca97d510803144d4c4122f2c11f86f84410a7af8..db504ec40cd9bd34d94d988ede92941a1bf2212f 100644 (file)
--- a/riscv/insns/c_sdsp.h
+++ b/riscv/insns/c_sdsp.h
@@ -1,3 +1,7 @@
-require_rvc;
-require_xpr64;
-mmu.store_uint64(XPR[30]+CIMM6*8, CRS2);
+require_extension('C');
+if (xlen == 32) {
+  if (sreg_t(RVC_RS1S) < 0) // c.bltz
+    set_pc(pc + insn.rvc_b_imm());
+} else {
+  MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
+}