Implement RVC draft

[riscv-isa-sim.git] / riscv / insns / c_slli.h

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
new file mode 100644 (file)
index 0000000..fb6dffd
--- /dev/null
+++ b/riscv/insns/c_slli.h
@@ -0,0 +1,4 @@
+require_rvc;
+if (insn.rvc_imm() >= xlen)
+  throw trap_illegal_instruction();
+WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));