Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / c_slli.h

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index fb6dffd3a331a2f88dec85b23415eccc42b10093..24fbb1335be3060dd7b9b1d2c2dd96a1585608ba 100644 (file)
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,4 +1,3 @@
-require_rvc;
-if (insn.rvc_imm() >= xlen)
-  throw trap_illegal_instruction();
-WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));
+require_extension('C');
+require(insn.rvc_zimm() < xlen);
+WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm()));