work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_slli.h

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index 50267679306e9a203da079c287b4af1c323ee24e..24fbb1335be3060dd7b9b1d2c2dd96a1585608ba 100644 (file)
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,5 +1,3 @@
-require_rvc;
-if(xpr64)
-  CRDS = CRDS << CIMM5U;
-else
-  CRDS = sext32(CRDS << CIMM5U);
+require_extension('C');
+require(insn.rvc_zimm() < xlen);
+WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm()));