Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / c_srai.h

diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h
index 87d7b5955272df1a1148df5643ee4b1d9b1f9cc6..f6638b1e2747c7bc2ec8bb268230658ff4f77052 100644 (file)
--- a/riscv/insns/c_srai.h
+++ b/riscv/insns/c_srai.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_imm() < xlen);
-WRITE_RD(sext_xlen(sext_xlen(RVC_RS1) >> insn.rvc_imm()));
+require(insn.rvc_zimm() < xlen);
+WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm()));