New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_srli.h

diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
new file mode 100644 (file)
index 0000000..bf29f5f
--- /dev/null
+++ b/riscv/insns/c_srli.h
@@ -0,0 +1,3 @@
+require_extension('C');
+require(insn.rvc_imm() < xlen);
+WRITE_RD(sext_xlen(zext_xlen(RVC_RS1) >> insn.rvc_imm()));