work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_srli.h

diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
new file mode 100644 (file)
index 0000000..f410fef
--- /dev/null
+++ b/riscv/insns/c_srli.h
@@ -0,0 +1,3 @@
+require_extension('C');
+require(insn.rvc_zimm() < xlen);
+WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm()));