Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / csrrsi.h

diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h
index 99d323bccf4d46d79afa390a18172436bb4e956b..aa44dcca8543ac374400450e4cc4326fc24652bc 100644 (file)
--- a/riscv/insns/csrrsi.h
+++ b/riscv/insns/csrrsi.h
@@ -1,2 +1,7 @@
-int csr = validate_csr(insn.i_imm(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) | insn.rs1()));
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
+reg_t old = p->get_csr(csr);
+if (write) {
+  p->set_csr(csr, old | insn.rs1());
+}
+WRITE_RD(sext_xlen(old));