New RDCYCLE encoding

[riscv-isa-sim.git] / riscv / insns / csrrw.h

diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index fbccb77466a1808bd6c4bc6748f09435c71054c2..4b16773d6cbc02dce6c20756412b322f4c983157 100644 (file)
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,2 +1,2 @@
-int csr = validate_csr(insn.i_imm(), true);
+int csr = validate_csr(insn.csr(), true);
 WRITE_RD(p->set_pcr(csr, RS1));