WIP on priv spec v1.9

[riscv-isa-sim.git] / riscv / insns / divuw.h

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index f52fe5a536834ef372ef8c7e8bb1526ca6678629..e127619aa990ad3394c16810268be611543ef221 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,8 @@
-RDR = sext32(uint32_t(RS1)/uint32_t(RS2));
-
+require_extension('M');
+require_rv64;
+reg_t lhs = zext32(RS1);
+reg_t rhs = zext32(RS2);
+if(rhs == 0)
+  WRITE_RD(UINT64_MAX);
+else
+  WRITE_RD(sext32(lhs / rhs));