[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / divuw.h

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 68f96a5d0768bf48451c93ee5ef99c2e78f27701..f52fe5a536834ef372ef8c7e8bb1526ca6678629 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA)/uint32_t(RB));
+RDR = sext32(uint32_t(RS1)/uint32_t(RS2));