Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / dret.h

diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h
index bef9ef2e26769c82fd37862cb3023de7e50f1d4b..35c19cb8a29090b774ff8c7a1fa091aa36428e21 100644 (file)
--- a/riscv/insns/dret.h
+++ b/riscv/insns/dret.h
@@ -1,9 +1,6 @@
 require_privilege(PRV_M);
 set_pc_and_serialize(STATE.dpc);
-/* The debug spec says we can't crash when prv is set to an invalid value. */
-if (p->validate_priv(STATE.dcsr.prv)) {
-  p->set_privilege(STATE.dcsr.prv);
-}
+p->set_privilege(STATE.dcsr.prv);
 
 /* We're not in Debug Mode anymore. */
 STATE.dcsr.cause = 0;