[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / ei.h

diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index 6d13be0d1dec960392435f3a9fa35f1502b43d32..f3e52075cc5c4f5550f6b884e7a07299ce978f9a 100644 (file)
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RT = temp;
+RDR = temp;