Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fadd_s.h

diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index 2fd5429c481d54f95087ba41460354ad66015c27..cc18d58cd6f4495f40fe72c065a8f025225c7d8d 100644 (file)
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,4 +1,5 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_add(FRS1, FRS2);
+WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;