Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fadd_s.h

diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index a35a5248872436e97b4667a811172c5627b62731..cc18d58cd6f4495f40fe72c065a8f025225c7d8d 100644 (file)
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));
+WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;